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modem/telephony codec ad1803 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features low power modem/telephony codec 16-bit oversampling - converter technology intel? ac 97 rev 2.1-compliant modem codec implementation ac 97 or dsp style serial interface supports all modem/fax standards, including v.90 multiple crystal/clock rates supported programmable gain, attenuation, and mute on-chip signal filters digital interpolation and decimation filters analog output low pass programmable sample rates from 6.4 khz to 16 khz with 1 hz, 8/7 hz, and 10/7 hz resolution digital codec engine with variable sample rate conversion digital monitor speaker output 24-lead tssop 0.6 m cmos technology operation from 3.3 v or 5 v supply advanced power management applications modems (pc and embedded) voice and telephony fax machines, answering machines, speakerphones pbx systems smart appliances functional block diagram ac'97/dsp serial port register control logic address register control registers avdd agnd dvdd dgnd bit_clk sync sdata_in sdata_out reset clk_out xtalo xtali dac filter - modulator dac filter + gain /atten adc filter pwm block general-purpose i/o g[4]/mout v ref g[1]/mic rx filt tx ad1803 voltage reference +20db mux g[0] g[2] g[3]/wake g[5] g[6] g[7] - adc 02562-001 figure 1. general description the ad1803 is a low power, 16-bit codec for modem, voice/handset, and telephony applications. it can also be used as a cellular telephone interface. the ad1803 is an intel ac '97 rev 2.1-compliant modem codec (refer to documentation about the intel ac '97) with selectable ac '97 or a dsp-style serial interface. the ad1803 codec uses high performance - adcs and dacs with programmable gain/attenuation. it has a digital - monitor output with selectable mix from adc and dac channels for call progress monitoring. the ad1803 supports advanced power management with several power saving modes. the codec supports seven general- purpose input/output (gpio) pins and a wake interrupt signaling mechanism on gpio events. the ad1803jruz is a lead-free environmentally friendly product. it is manufactured using the most up-to-date mate rials and processes. the coating on the leads of each device is 100% pure tin electroplate. the device is suitable for lead-free applications and can withstand surface-mount soldering at up to 255c (5c). in addition, it is backward compatible with conventional tin-lead soldering processes. this means that the electroplated tin coating can be soldered with tin-lead solder pastes at reflow temperatures of 220c to 235c.
ad1803 rev. a | page 2 of 32 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 test conditions............................................................................. 3 typical supply current ................................................................ 5 timing specifications .................................................................. 6 timing diagrams.......................................................................... 7 absolute maximum ratings............................................................ 8 environmental conditions.......................................................... 8 package characteristics ............................................................... 8 esd caution.................................................................................. 8 pin configuration and function descriptions............................. 9 theory of operation ...................................................................... 11 serial interface mode selection................................................ 11 serial interface behavior and protocol when in ac '97 mode ............................................................................................ 11 ac '97 interface modes ............................................................. 11 serial interface behavior and protocol when in dsp mode 12 register banks............................................................................. 14 register access restrictions...................................................... 14 general-purpose i/o pin operation ....................................... 14 control register map..................................................................... 15 control register details................................................................. 17 extended modem id register .................................................. 17 extended status and control register..................................... 17 line dac/adc sample rate control register ..................... 18 dac/adc level control register........................................... 19 gpio pin configuration register............................................ 20 gpio pin polarity/type register ............................................. 20 gpio sticky pin register .......................................................... 20 gpio pin wake-up mask......................................................... 21 gpio pin status register .......................................................... 21 miscellaneous modem afe status and control register..... 21 configuration 1 register ........................................................... 22 configuration 2 register ........................................................... 23 bank 1gpio initial states register ...................................... 24 bank 1clock pad control register ...................................... 24 bank 2 - monitor output control register ............................ 25 version id register .................................................................... 25 vendor id1 register .................................................................. 26 vendor id2 register .................................................................. 26 applications..................................................................................... 27 application circuits ................................................................... 27 typical initialization sequence immediately after first reset .......................................................................................... 29 typical codec power-up sequence ......................................... 30 typical codec power-down sequence.................................... 31 typical chip power-down sequence ...................................... 31 outline dimensions ....................................................................... 32 ordering guide .......................................................................... 32 revision history 12/06rev. 0 to rev. a updated format..................................................................universal changes to figure 18...................................................................... 28 changes to ordering guide .......................................................... 32 8/01revision 0: initial version
ad1803 rev. a | page 3 of 32 specifications test conditions test conditions for the ad1803 are as follows, unless otherwise noted. general test conditions temperature at 25c digital supply at 3.3 v/5 v analog supply at 3.3 v/5 v sample rate (f s ) at 8 khz input signal at 1008 hz analog output pass band at 20 hz to 4 khz adc fft size at 512 dac fft size at 4096 v ih @ 2.1 v v il @ 1.2 v v oh @ 2.9 v v ol @ 0.3 v i oh @ ?2.0 ma i ol @ +2.0 ma dac output test conditions 0 db attenuation relative to full scale input 0 db mute off 10 k output load adc input test conditions autocalibrated 0 db pga gain mute off input: 1.0 db relative to full scale table 1. parameter test conditions/comments min typ max unit adc receive path full-scale input voltage 1 pga gain = 0 db, offset error = 0% of fs 1.56 v rms ad1803 rx input 0 dbm 2.1 2.2 2.3 v p-p resistancerx input 2 0 db gain 110 k +20 db gain 10 k capacitancerx input 2 15 pf rx programmable gain gain step size 3 0 db to 42.5 db 1.0 1.5 2.0 db input gain span 4 41.5 42.5 43.5 db analog-to-digital converter dynamic range 5 ?60 db input, pga gain = 0 db 85 90 db dynamic range 2, 5 ?60 db input, pga gain = 6 db 90 db dynamic range 2, 5 ?60 db input, pga gain = +12 db 90 db thd + n ?1 db input referenced to full scale ?90 ?85 db signal-to-intermodulation distortion 2 ccif method 80 db offset error 0 v analog input, pga gain = 0 db 1 5 % of fs dac transmit path digital-to-analog converter dynamic range 5 ?60 db input, output ga in = 0 db 85 db thd + n ?1 db input referenced to full scale ?75 db signal-to-intermodulation distortion 2 ccif method 80 db total out-of-band energy 2 measured from 0.555 f s to 100 khz ?40 db dc offset 100 mv programmable gain/attenuator step size 3 +12 db to ?34.5 db 1.0 1.5 2.0 db output attenuation span 45.5 46.5 48 db full-scale output voltage tx output 0 dbm 2.1 2.2 2.3 v p-p tx pin capacitance 15 pf tx load capacitance 100 pf
ad1803 rev. a | page 4 of 32 parameter test conditions/comments min typ max unit monitor output digital-to-analog converter dynamic range 2, 5 ?60 db input, a-weighted 50 db thd + n 2, 5 0.316 1 % ?50 ?40 db programmable gain/attenuator step size 2 ?18 db to +45 db 2.4 3.0 3.6 db output attenuation span 2 63 db digital decimation and interpolation filters 2 pass-band edge ?0.22 db point 0.445 f s hz pass-band ?3.0 db point 0.490 f s hz pass-band ripple 0.0 ?0.2 db transition band 0.445 f s 0.555 f s hz stop-band edge 6 0.555 f s hz stop-band rejection plus 3 db roll-off 78.0 db group delay 21/f s s group delay variation over pass band 0 khz to 4 khz 0.45 s 0 khz to 8 khz 1.30 s sample rate 6.4 16 khz static digital v ih , high level input voltage digital inputs 0.65 dvdd v v il , low level input voltage 0.35 dvdd v v oh , high level output voltage i oh = ?0.5 ma 0.9 dvdd v v ol , low level output voltage i ol = +0.5 ma 0.1 dvdd v input leakage current ?10 +10 a output leakage current ?10 +10 a power supply avdd range 3.3 v/5 v 3.0/4.75 3.6/5.25 v dvdd range 3.3 v/5 v 3.0/4.75 3.6/5.25 v analog and digital supply current 5 v, see table 2 analog and digital supply current 3.3 v, see table 2 power supply rejection 7 100 mv p-p, signal @ 1 khz 40 db clock input clock frequency 12.288 24.576 32.768 mhz recommended clock duty cycle 45 50 55 % 1 rms values assume sine wave input. 2 guaranteed by design, not production tested. 3 all steps tested. 4 the adc gain is achieved using a 0 db to 22.5 db variable gain stage and a 20 db fixed gain stage. the 22.5 db to 42.5 db gain steps are achieved by enabling the 20 db gain stage. 5 thd + n referenced to full scale. 6 the stop band repeats itself at multiples of 64 f s , where f s is the sampling frequency. the digital filter attenuates to ?78.0 db or better across the frequency spectrum, except for a range 0.555 f s wide at multiples of 64 f s . 7 at both analog and digital supply pins (both adcs and dacs).
ad1803
ty pical su pply curre nt t y p i c a l sup p ly c u r r e n t is for mo st c o m m on mo de s of op e r a t ion . a l l c u r r e n ts in ma , u n l e ss ot he r w is e note d. table 2. resour c e 3.3 v 5.0 v regist er w r it es t o en t er mode gpio w eak p u ll-up c u r r en t per p in rese t is asser t ed x t ali o ff ( a ll d o wn) 1 x t ali enabled: nominal p o w e r x t ali enabled: l o w p o w e r clk_out p in running 2 rese t is d e asser t ed and analog and digital c o dec in f u ll p o w er m o d e spor t and clk _out a c tiv e 2, 3 x t ali in l o w p o w e r m o de 2, 3 clk_out i n ac tiv e (l o w ) 3 v ref po w e r e d u p 3 adc enabled d a c enabled 3, 5 adc + d a c ena b led 3, 5 adc, d a c, + m o n enabled 3, 4, 5 adc, d a c, + m o n enabled 3, 5, 6 ~ 100 <30.0 1.4 1.0 1.6 2.6 2.2 1.7 1.9 7.3 8.2 9.2 9.3 10.2 ~ 140 a <40.0 a 2.4 1.7 3.2 6.4 5.7 4.3 4.5 12.4 13.7 14.7 14.9 16.3 default settings af t e r po w e r - on rese t default settings af t e r po w e r - on rese t 5c:r34p4 = 1 5c:r34p4 = 1, 6 4b1:x tlp = 1 5c:clkea = 1 default settings af t e r po w e r - on rese t 64b1:x t lp = 1 5c:clked = 0 3e:vpdn = 0 3e:apdn = 0 3e:dpdn = 0 3e:apdn = dpd n = 0 3e:apdn = dpd n = 0, 5e:gp m o n = 1 3e:apdn = dpd n = 0, 5e:gp m o n = 1 1 a ssum e s a l l i n put s a r e st a t i c (n ot swi t ch i n g) a n d a l l out p u t loa d s a r e ca pa ci t i ve (n on re si st i v e).
2 exc l udes current drawn by clk _ out pin board loading.
3 a ssum e s t h e seri a l i n t e rfa c e i s c o n f i g u r ed i n ac '97 pri m a ry m o d e wi t h 20 pf loa d s on t h e sd at a_in pi n a n d bit_ c l k pi n . typi ca l current is approximatel y 0.8 ma less if the
serial interface is co nfigured in dsp mo de with 20 pf loads on the sync pin, bi t_clk pin, and sd ata_in pin (du e to a lower bit _ clk freq uency). 4 a ssum e s a 20 pf lo a d on t h e g[4 ] /mo u t pi n . 5 assumes no dac load, 0. 6 ma shou ld be added if a 600 loa d is u s ed. 6 assumes the g[4 ] / m out pin is loa d ed with a 1 k resi stor in seri es with a parallel 4.7 k r e si stor and 100 nf capacitor combin atio n tie d to d igital gro u nd . this f i l t e r, with the output taken fr om the middle node, has a 1500 hz corner to filter out high-frequency - noise. it generates an ap proximate 1 v p-p output when us ing a 5 v d i gital suppl y with the monitor output conf igured a s first o r de r (bit mmd1 and bit mmd0 set to 10 in regi ster 0x 60 bank 2) if the filter outpu t l o ad is gre ate r than o r e q ual to 20 k . r e v. a | pa ge 5 o f 3 2
ad1803
timing spe cific ations table 3. p a r a me t e r 1 s y mbol m i n t y p ma x unit serial por t a c '97 mode rese t ac t i ve low pu l s e wi d t h t rst _ l o w 1.0 s rese t i n ac tiv e to bit_clk star t-up d e la y t rst 2 clk 162.8 ns s y n c ac t i ve h i g h pu l s e wi d t h ( w a r m r e s e t ) t syn c _high 1.3 s sy nc i n ac tiv e to bit_clk star t-up d e la y ( w ar m rese t ) t syn c 2clk 162.8 ns bit_clk f r eque nc y 12.288 mh z bit_clk p e r iod t clk _ period 81.4 ns bit_clk o utput j i tt er 2 750 ps bit_clk h igh p u lse w idth t clk _ high 36.62 40.69 44.76 ns bit _clk l o w p u lse w i d t h t clk _ l o w 36.62 40.69 44.76 ns sy nc f r equenc y 48.0 kh z sy nc p e r i od t syn c _period 20.8 s s e tup t o f a lling e d ge of bit_clk t se t u p 10.0 ns hold fr om f a lling e d ge of bit_c l k t hold 10.0 ns p r opaga ti on d e l a y t co 15 ns bit_clk r ise t i me t riseclk 2 4 6 ns bit_clk f a ll t im e t fa l l c l k 2 4 6 ns sy nc r ise t ime t risesyn c 2 4 6 ns sync f a ll t ime t f a llsyn c 2 4 6 ns sd a t a_in r i se t ime t ri sedi n 2 4 6 ns sd a t a_in f a ll t ime t f a lldin 2 4 6 ns sd a t a_out r i s e t ime t ri sedou t 2 4 6 ns sd a t a_out f a ll t ime t fa l l o u t 2 4 6 ns end of slot 2 t o bit_clk , sd a t a _ in l o w (m lnk s e t) t s2_pdo wn 2 1000 ns setup t o t r ailing e d ge of rese t ( a pplies t o sy nc, sd a t a_out ) t se t u p2rst 15 ns r i sing ed g e of r e s e t to h i-z d e la y ( a te t e st m o d e ) t of f 25 ns serial por t dsp mode rese t ac t i ve low pu l s e wi d t h t rst _ l o w 1.0 s rese t i n ac tiv e to bit_clk star t-up d e la y t rst 2 clk 162.8 ns bit_clk f r eque nc y 4.096 mh z bit_clk p e r iod t clk _ period 244.14 ns bit_clk o utput j i tt er 2 750 ps sy nc f r eq uenc y 8 kh z sy nc p e r i od t syn c _period 125 s s e tup t o f a lling e d ge of bit_clk t se t u p 10.0 ns hold fr om f a lling e d ge of bit_c l k t hold 10.0 ns p r opaga ti on d e l a y t co 15 ns bit_clk r ise t i me t riseclk 2 4 6 ns bit_clk f a ll t im e t fa l l c l k 2 4 6 ns sy nc r ise t ime t risesyn c 2 4 6 ns sync f a ll t ime t f a llsyn c 2 4 6 ns sd a t a_in r i se t ime t ri sedi n 2 4 6 ns sd a t a_in f a ll t ime t f a lldin 2 4 6 ns sd a t a_out r i s e t ime t ri sedou t 2 4 6 ns sd a t a_out f a ll t ime t f a lldou t 2 4 6 ns s e tup t o t r ailing e d ge of rese t ( a pplies t o sy nc , sd a t a_out ) t se t u p2rst 15 ns r i sing e d ge of r ese t t o h i -z d e l a y ( a te t e st m o de) t of f 25 ns 1 guaran t eed over o p erat in g t e mperature range and supply pow e r. 2 output jitte r is d irectl y de pe nd e nt o n crys tal input jitte r. r e v. a | pa ge 6 o f 3 2
ad1803
timing diagrams bi t _ cl k t r s t_ lo w t rs t 2 cl k t r i secl k t fa llc lk re s e t 02 562 - 00 4 02 56 2- 00 2 02 56 2- 00 3 02 56 2- 00 5 t r i sesy n c t r i sedi n t fa lls y n c t falld i n bi t _ cl k sy n c figure 2. cold reset s d at a_i n t s y n c_ hi g h t syn c2clk sy n c sd a t a _ o u t t ri s e do ut t fa lld o u t 0 25 62 - 00 6 0 25 62 - 0 07 bi t _ cl k figure 3. warm reset figure 6. sign al ris e and fa ll ti me t cl k_ l o w bi t _ cl k t c l k_ hi g h t s y nc_ hi g h t cl k _ p e ri o d t syn c _ l o w t syn c_pe r i o d bi t _ c l k sy n c sd a t a _ i n t co figure 4. clock t i ming fig u re 7. p rop ag at i o n d el a y sl o t 1 sl o t 2 wr it e t o 0x56 da t a mln k do n t ca re t s 2_p d o w n syn c bi t _ cl k t set up bi t _ cl k s d at a_o u t syn c t ho ld s d at a_o u t sd a t a _ i n no t e s 02 56 2- 00 8 1. bi t _ cl k i s no t t o s cal e . figure 5. dat a s e tup and hold figure 8. ac link l o w power mod e t i ming r e v. a | pa ge 7 o f 3 2
ad1803
absolute maximum ra tings
table 4. p a r a me t e r r a ting p o w e r suppl ie s digital ( d vdd) ?0.3 v to +6.0 v analog ( a vdd ) ?0.3 v t o +6.0 v i n put c u rr en t (e x c ept supply p i ns) 10.0 ma analog i n put v o ltage ( s ignal p ins) ?0.3 v to a v dd + 0.3 v digital i n put v o l t age ( s ignal p ins) ?0.3 v to dvdd + 0.3 v o p era t ing ambi en t t e mpera tur e 0c to 70c stor age t e mpera tur e ?65c to +150c s t r e s s es a b o v e t h os e list e d u nde r a b s o l u te m a xi m u m r a t i n gs ma y ca us e p e r m a n e n t dama ge to t h e de vi ce. t his is a st r e ss r a t i ng on ly ; f u n c t i on a l op e r at i o n of t h e d e v i c e a t t h e s e or an y o t h e r con d i t ions a b o v e t h o s e i ndic a te d i n t h e op er a t io na l s e c t io n o f t h is sp e c if ic a t io n is no t im pl ie d . e x p o sur e t o a bs o l u te max im u m r a t ing co ndi t ion s fo r ex tende d p e r io d s ma y a f fe c t de vice rel ia b i l i t y . enviro nme n tal co nditio ns ambi ent t e m per at ure r a ti ng t am b = t ca s e ? ( p d ca ) w h er e:
t ca s e is t h e cas e t e m p era t ur e in c,
p d is t h e p o w er dissi p a t io n in w ,
ca is t h e t h er mal r e sis t a n c e (cas e-t o - a m b ien t ),
ja is t h e t h er mal r e sis t a n c e (j u n c t ion- t o -am b i e n t ),
jc is t h e t h er mal r e sis t a n c e (j u n c t ion- t o -cas e).
package c h aracteristics table 5. p a ck age ja jc ca tssop 83.8c/w 15.6c/w 68.2c/w esd caution
r e v. a | pa ge 8 o f 3 2
ad1803
pin conf igura tion and function descriptions
cl k _ o ut 1 2 3 4 5 6 7 8 9 10 21 22 23 24 20 19 18 17 16 15 14 13 12 11 a d 180 3 t o p vi ew (n o t to sc al e ) g[ 5 ] dg nd g[ 6 ] dv dd g[ 7 ] xt a l o av dd xt a l i tx bi t _ cl k ag nd s dat a_i n v ref s dat a_o u t fil t sy n c rx re s e t g[ 1 ] /m ic g[ 4 ] / m ou t g[ 0 ] g [ 3] / w ake g[ 2 ] figure 9. pin c o nfiguration ta ble 6. pi n f u nct i on d es c ri pt i o ns 02 56 2- 00 9 m nemonic p i n no . i/o description anal og sign a l s dvdd dgnd a v dd a gnd rx t x fil t v ref 3 2 21 19 16 20 17 18 i i i i i o i i dig i tal supply . r a nge: 5.0 v 10 % or 3.3 v 10 % (independen t of a v dd ). dig ital gr ound . must be a t same poten tial as a g nd . analog supply . r a nge is 5.5 v th r o ugh 3.0 v (ind ependen t of dvdd ). analog gr ound . must be a t same poten tial as dg nd . r e c e iv e ( a dc ) i n put. t r ansmit (d a c ) output. adc f ilter bypass . r e quir e s 1 f capacitor to a g nd . v o ltage r e f e r e nc e . r e quir es 1 f capacitor to a g nd . cl ock signals x t ali x t al o clk_out 5 4 1 i o o cr ystal or clock i n put (12.2 88 mh z, 24.576 mh z, or 32.768 mh z). this clock input is nec e s- sar y only if the ad1803 is c o nfigur ed in either a c '97 pr imar y or dsp mode , or if a w a ke in t e rrupt fr om an ev en t is r e q u ir ed (in an y mo de ). this pin must be tied to dvdd or dgnd (not floa ted) when cloc k input is not nec ess ar y . i f a cr ystal is used , it must be paralle l re s o n a n t firs t harmonic , an d ti ed bet w een this p in and the xt a l o p in wi th loa d capa cit a n c e specified b y the cr ystal sup p li er . s ee the x t al1 bit and the xt al0 bit in r e gister 0 x 5c f o r fur t her de tails . cr y s tal o utput. t h is pin should be floa t e d when a cr y s tal is not used . buff er ed v e rsio n of clock p r esen t on the x t ali pin, unless disa ble d . s ee the clked bit and clkea bit in r e g i st er 0x5c f o r fur t her details . serial i nte rf a c e signals 1 rese t bit_clk sy nc sd a t a_in sd a t a_out 10 6 9 7 8 i i/o i/o o i a c tiv e l o w p o w er-d o wn. l ev e l of po w er- d o wn is d eter mined b y bits in r egister 0x5c. this pin must be ass er t ed (d r iv en low) as pow er is fi rst ap plied un til the sup p ly is sta b le . the ad1803 is rese t ex clusiv ely b y an in t e rnal pow er - o n rese t cir c uit. s e r i al da ta clock . o utput if the ad1803 c o nfigur ed in a c '97 pr imar y or dsp mode . i n put if the ad1803 is c o nfigur ed in an y a c '97 sec o ndar y mode . s e r i al da ta f r am e s y nc . o utput i f the ad1803 is c o nfigur ed in dsp mode . i n put i f the ad1803 is c o nfigur ed in an y a c '97 mode . s e r i al da ta o utput fr om ad1803 . s e r i al da ta i n put to ad1803. r e v. a | pa ge 9 o f 3 2
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m nemonic p i n no . i/o description general - pu rp ose i/o and barrier interf a c e sign als 2 g[0] 3, 4 g[1]/mic 3, 5 g[2] 3, 4, 6 g[3]/w ake 3, 4, 6 g[4]/mout 3, 4 g[5] 3, 4 g[6] 3, 4 g[7] 3, 4 14 15 13 12 11 24 23 22 i/o i i i/o i/o o i/o o i/o i/o i/o g eneral-p u r pos e i/o . g e ner a l-p u r pose i/o . analog mic i n put. s ee bit gp mi c in r e g i st er 0x5e . g eneral-p u r pos e i/o . also used to selec t ser ia l in ter f ac e mod e . g eneral-p u r pos e i/o . w a ke i n t e rrupt o utput (see the gpw a k bit in r e g i st er 0x 5e). t h i s pin selec t s the serial in ter f ac e mode . w h en ser ving a s w a ke, this pin is driv en high if selec t ed gpio pins r e ceiv e selec t ed logic le v el s ( s ee r egister 0x52 and r egister 0x4e) . g eneral-p u r pos e i/o . m o nit o r o utput. see the c o nfigur a t ion 2 r e g i st er sec t ion. g eneral-p u r pos e i/o . g eneral-p u r pos e i/o . g eneral-p u r pos e i/o . 1 s e e the g[ 3]/wake pin and the g[ 2] pi n f o r se rial inte rf ace mod e s e l e ctio n.
2 se e r e gi st er 0x4 c t h rough r e gi st er 0x 54 a n d ba n k 1 r e gi st er 0x60 for t h e g e n e ra l- purpose i/o p i n con t r ol.
3 by d e f a ul t the g[ 7 ] pin, g[ 6] pin, g[ 5 ] p i n, g[ 4] pin, g[ 3 ] pi n, g[ 2] pin, and g[ 1 ] pin se rve as inputs with we ak (~ 30 k e q ui va len t ) i n t e r n a l pull- up devi ce s en a b led.
4 input voltage on t h e g[7 ] pin, g[6] pin, g[5] pin, g[4] pin , g[3 ] pi n, g[ 2] pin, and g[ 0 ] pin mus t no t e x ce ed dvdd b y mo re tha n 0.3 v.
5 in put volt a g e on pi n g[1] m u st n o t e x ce e d avdd by mo re than 0 .3 v.
6 th e st a t es o f t h e g [ 3/wa ke ] pi n a n d g [ 2] pi n a r e sa m p l e d wh en re se t is dea sserted (driven fr om low t o high) for the fir s t time after pow e r is applied to se lect ad1803 serial
interface mode. on ce sampled, serial i nterface mode can be changed only b y removing pow e r from the ad1803. g[3]/wake g[2] s e r i al inter face mod e hi gh /hi g h ac 97 mod e , pri m a ry devi ce ( i d : 00) hi gh low ac 97 mod e , sec o n d a ry d e vi ce ( i d : 01) low hi gh ac 97 mod e , sec o n d a ry d e vi ce ( i d : 10) low low dsp mode rev. a | page 10 of 32
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theor y of opera tion serial inte rface mode selection b y defa u l t t h e ad1803 us es s lo t 5 t o s e nd and r e cei v e s a m p le w h en p o w er is f i rs t a p p l ie d t o t h e ad1803, res e t mu s t b e da ta , b u t this can b e c h a n g e d t o s lo t 10 o r s lo t 11. s e e t h e ass e r t e d ( res e t p i n d r i v en lo w), and k ep t ass er t e d u n t i l t h e sp c h n bit , sp g b p bit , s p d s s bit , sp i s o bit , sp dl 1 bit , a n d s p d l 0 b i t in reg i s t er 0x5e f o r addi tio n al a c '97 m o de co n- po w e r h a s s t a b ili z e d . w h ile res e t is as s e r t ed , t h e ad1803 s f i gura ti o n e nha n c em en t s . s e r i al in t e r f ace m o de is ch os en b y t h e s t a t e o f p i n 12 (g[3]/w a k e) a n d p i n 13 (g[2]). ac '97 inte rface modes table 7. primary mo de p in 12 p in 13 mode chosen h i gh h i gh l o w low h i gh l o w h i gh low a c '97 m o de p r imar y d evic e (i d: 00) a c '97 m o de sec ondar y devic e (id: 01) a c '97 m o de sec ondar y devic e (id: 10) d s p m o d e en ter e d if g[ 3] p i n and g[ 2] p i n a r e hig h w h e n t h e res e t pi n i s d e a s s e r t ed f o r th e f i r s t tim e : ? ad1803 is t h e t i min g mas t er : dr i v es b i t_ clk a t 12.288 mh z. n o te t h a t pi n 1 2 a nd pin 13 h a ve w e a k p u l l -u p de vices in ter n a l ? ad1803 accep t s th e 48 kh z s y n c timin g s i g n al .
t o th e ad1803 t h a t a r e enab led b y def a u l t. th er ef o r e , if th es e
pi ns are f l o a te d, a c ' 9 7 pr i m ar y mo d e i s c h o s e n . whe n res e t ? ad1803 r e q uir es a cr ys tal o r c l o c k o n xt ali (s ee the
is de ass e r t e d ( res e t p in dr i v en hig h) fo r t h e f irst t i me a f ter xt al1 b i t and xt al0 b i t in reg i s t er 0x5c f o r f r eq uen c y).
p o w er is a p pli e d , t h e st a t e s o f pin 12 and pin 1 3 a r e la tch e d ,
secon d ary mo de lo ck in g i n s er i a l in t er f a c e m o d e . s u bs e q ue n t chan ges o f t h e lo g ic le vel p r es e n te d o n pi n 12 a nd pin 13 h a ve n o ef fe c t o n en ter e d if t h e g [ 3] p i n is hig h and g[ 2] p i n is l o w w h e n t h e s e r i al p o r t m o de un til p o w e r is r e m o v e d f r o m t h e ad1803. res e t p i n is deas s e r t e d f o r th e f i rs t t i m e o r if t h e g[3] p i n is af t e r t h is f i rst d e ass e r t io n o f res e t , pin 12 and pin 1 3 t a k e lo w an d t h e g[2] p i n is hig h w h en t h e res e t pi n i s d e a s s e r t e d o n ne w r o les and s e r v e as g e n e ral-p u r p os e i/o co n t r o l p i n s. f o r th e f i r s t tim e : the ad1803 do es n o t n e e d an ac ti v e c lo c k s o ur ce f o r p r o p er ? ad1803 is t h e t i min g sla v e: acc e p t s b i t_clk a t o p er a t ion d u r i ng t h is m o de s e le c t io n. 12.288 mh z. serial inte rface beh avi or an d prot ocol when in ac '97 mode ? ad1803 accep t s th e 48 kh z s y n c timin g s i g n al . the ad180 3 s e r i al in t e r face is com p a t ib l e wi t h t h e a c '9 7 ? ad1803 do es no t r e q u ir e a cr ys tal o r c lo c k o n xt ali r e v 2 .1 sp e c if i c a t ion as ei t h er a p r ima r y o r a s e conda r y (s ee t h e xt al1 b i t and xt al0 b i t in reg i s t er 0 x 5c f o r mo de m / h a n d s et co d e c d e v i c e. c o n s u l t t h i s sp e c if ic a t ion f r eq ue n c y), unl e s s w ak e f r o m a n ev en t d u ri n g res e t is f o r co m p let e b e ha vi o r al deta ils. desir e d . xt ali oka y h e r e ? sl o t # 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 syn c cm d addr cm d dat a ta g p c m l pc m r lin e 1 dac pc m ce nt e r pc m l s u r r pc m r s ur r pc m lf e li n e 2 da c h set dac i/o ct rl 02 56 2- 0 10 s da t a _ o u t ( o ut p u t f r o m c o n t ro l l e r / d s p C i n p u t t o ad1803) ( i np u t t o co nt ro l l e r / d s p C o u t p u t f r o m ad1803) fi gur e 10 . ac '9 7 inte r f a c e ti mi ng s t at us addr s t at us da t a ta g m i c ad c li n e 2 ad c rs rv d rs rv d rs rv d hs e t ad i/ o s t at us pc m l pc m r lin e 1 adc sd a t a _ i n rev. a | page 11 of 32
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serial inte rface beh avi or an d prot ocol when in ds p mo de i n ds p m o de , t h e ad1803 r e q u ir es a c lo c k on xt ali t o f u n c - t i o n p r o p erly . t h is clo c k can b e cr e a t e d b y plac i n g a cr y s t a l b e tw e e n pi n x t ali an d pi n x t alo w i t h a p p r o p r ia t e t r i m ca p a ci to rs. a l te r na t i vely , a clo c k can b e dr i v e n dir e c t ly o n to th e xt ali p i n f r o m a n ext e r n al s o ur ce , in which cas e xt al o m us t be f l o a t e d . w h en th e ad1803 s e r i al in t e rfac e is co n f ig ur ed i n ds p m o de , t h e clo c k p r es en t e d o n t h e x t a l i pin is ass u m e d t o be 24.576 m h z. h o w e v e r , a 12. 288 mh z o r 32. 768 mh z c lo c k co uld b e used in s t ead , p r o v id in g ? a r e g i s t er wr i t e inf o r m s the ad1803 o f th e tr ue c lo c k f r eq uen c y bef o r e the co dec is ena b led . ? i t is accep t ab le to ha v e t h e s er i al p o r t b i t c l o c k and f r a m e sy n c r u n a t r a te s dif f er en t f r o m t h e st a r t-u p n o mina l u n t i l t h e ad1803 i s in f o r m ed o f th e tr ue xt ali c lo c k f r eq uen c y . wi t h i n 1 m s a f t e r res e t is de ass er t e d a nd t h e a d180 3 r e cei v es a c lo c k o n xt ali, the ad1803 beg i n s dr i v in g a 4.096 mh z b i t c l o c k o n t o t h e b i t_ clk p i n ( a s s u min g a 24.5 76 mh z xt ali c lo c k). a p p r o x ima t e l y 100 s la t e r , the ad1803 beg i n s dr i v in g a n 8 k h z f r am e sy n c o n t o t h e s yn c pin ( a ga i n assumi n g a 24.576 mh z xt ali c lo c k). i f t h e ad1803 r e ceiv es a n xt ali c l o c k t h a t i s high er/lo w e r t h a n th e exp e c t e d 24. 576 mh z defa u l t, t h e s e f r eq ue n c i e s a r e scal ed u p / d o w n (l i n eall y ) u n til th e a d 18 03 is inf o r m ed o f t h e ac t ual xt al i c lo c k f r eq uen c y b y a wr i t e t o th e xt al1 and xt al0 b i ts in reg i s t er 0x5c. s e e the xt al1 a nd x t al0 b i ts fo r f u r t h e r det ai l s in cl u d i n g a l l o w e d a l ter n a t e xt ali f r e q uencies. e a c h s e r i al in ter f ace f r a m e con sis ts o f a sin g l e 1 6 -b i t w o r d s e n t in t o t h e ad180 3 o n the s d a t a_o u t p i n, and a sin g le 16-b i t w o r d s e n t o u t o f th e ad1803 o n th e s d a t a_in p i n. th es e w o r d s are s i m u lt a n e o u sly t r ans f e r re d d u r i ng t he f i rst 1 6 cl o c k s of t h e bi t _ c l k pi n af te r t h e st ar t of a f r ame. t h e st ar t of a f r ame i s ma rk e d b y o n e bit_ clk lo n g hig h p u ls e o f t h e s ync p i n o n e b it_ clk p e r i o d b e f o r e th e f i rst b i t in t h e f r a m e . da t a is tra n s - mi t t e d ms b f i rst. l o g i c leve ls o n al l p i n s (s ync, s d a t a_in, a nd s d a t a_ ou t) a r e u p da te d o n bi t_ clk r isin g e dges, and shou l d b e s a m p l e d on bi t _ c l k f a l l i n g e d ge s . by defa u l t, a l l f r a m es a r e desig n a t e d as da t a f r a m es fo r deliver y o f tw o s com p le m e n t d a c an d ad c s a m p les to a n d f r o m t h e ad1803 co dec. t o de li v e r con t r o l inf o r m a t io n in t o t h e p a r t , th e ls b o f t h e w o r d in t o the ad1803 is s t olen, f r o m wha t m i g h t o t h e rw i s e h a v e b e e n d a c d a t a , t o s e rv e a s a c o n t r o l f r a m e r e q u es t b i t. w h ile t h e ad1 803 p r o v ides 16 -b i t ad c s a m p l e o u t p u t , o n l y 15-b i t d a c s a m p le in p u t is p o ss i b le b e ca us e o f t h is. i f t h e ls b o f th e w o r d in t o th e ad1803 is s e t t o 0, n o co n t r o l f r a m e is r e q u es t e d and t h e n e xt f r a m e is a n o t h e r da t a f r a m e. i f t h e ls b o f th e w o r d in t o t h e ad180 3 is s e t t o 1, a con t r o l f r a m e is r e q u es t e d and t h e n ext f r am e is a co n t r o l f r a m e . w h en a co n t r o l f r a m e is r e q u es te d , a n ext r a f r a m e is in s er t e d b e tw e e n da t a f r a m es a v o i din g an i n ter r u p t i o n of co de c s a m p le da ta f lo w . th e 1 6 -b i t co n t r o l w o r d in t o the ad1 803 co n sis ts o f (f r o m ms b t o ls b): ? a re g i ste r re a d / w r i t e re qu e s t bit ( 0 to re qu e s t a w r it e, 1 to re qu e s t a re a d ) . ? the 6 ms bs o f a 7-b i t r e g i st er addr es s (w h e r e t h e lsb is r e m o v e d t o s a ve s p ace sin c e i t is al wa ys a 0). ? a b y te s e le c t b i t (0 t o s e le c t t h e lo w e r b y t e o f t h e 16-b i t co n t r o l r e g i s t er addr ess e d , 1 t o s e le c t t h e u p p e r b y t e o f t h e 16 -b i t con t r o l r eg i ster addr e s s e d). ? e i g ht b i ts o f da t a t ha t a r e wr i t ten i n to t h e addr essed r e g i st e r if a wr i t e is r e q u es t e d . o t h er w is e , t h es e las t e i g h t b i ts a r e i g nore d. w h i l e i t s e em s p e c u lia r t o ha v e a 7-b i t r eg i s t e r addr es s wi t h th e ls b dr o p p e d wh en s e n t t o th e ad1803, i t s h o u ld be n o t e d t h a t ad1803 r egis t er addr es ses a r e def i n e d b y t h e a c '97 s p e c i f i c a - tio n , wh eth e r c o nf i gu r ed in a n a c '97 m o de o r in ds p m o de . w h i l e t h e a c 97 re v 2. 1 s p ecif ica t io n r es e r v es o dd add r es s e s f o r f u t u r e fe a t ur e exp a n s io n, t h er e was n o r o o m i n t h e ds p m o d e c on t r o l wo rd f o r t h i s u n u s e d bi t . t h e 1 6 - bit co n t rol word out o f t h e ad 1803 co n s is ts o f , f r o m ms b t o ls b , eig h t un us e d b i ts t h a t a r e a l wa ys s et t o 0, f o llo w ed b y eig h t b i ts o f da t a t h a t r e f l e c t t h e co n t en ts o f th e r eg i s t e r addr e s s e d wi t h in t h e c u r r e n t f r a m e , i f a r e ad wa s r e q u est e d . o t h e r wise, t h e y a r e al l set t o 0. w h en s e r i al i n ter f ace f r a m es f i rs t co mm e n ce af t e r res e t is deas s e r t ed , t h ere a r e 512 b i ts p e r f r a m e (8 kh z f r a m e ra t e / 4.096 mh z b i t clo c k ra t e ) w h er e o n l y th e f i rs t 1 6 b i ts p e r f r a m e a r e typ i cal l y u t il ize d . b i ts o u t o f th e ad1803 a f ter th e f i rs t 16 a r e typ i cal l y s e t t o 0, a nd b i ts in to th e ad1803 af t e r th e f i rst 16 a r e typ i cal l y ig n o r e d . h o w e v e r , w h en a co n t r o l f r a m e is r e q u es t e d v i a t h e co n t r o l f r a m e r e q u est b i t in a da t a f r a m e , t h e con t r o l f r a m e is ins e r t e d b e tw een da t a f r a m es a nd p lac ed 256 b i ts a f t e r t h e s t a r t o f t h e da t a f r am e t h a t r e q u es t e d t h e c o n t r o l f r a m e . this c o n t rol f r ame i s m arke d b y an a d d i t i on a l 1 - bi t l o ng cl o c k pu l s e, h i g h o f t h e s y n c p in. n o te tha t t h e sp acin g b e tw e e n da t a f r a m es is ne v er a f fe c t e d b y t h e i n s er t ion o f a co n t r o l f r a m e. rev. a | page 12 of 32
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the f r a m e ra t e a t s t a r t u p is 8 kh z and t h er e a r e exac tl y 512 b i ts f r o m t h e s t a r t o f o n e da t a f r a m e t o t h e n ext; t h i s c h a n g e s a s s o o n as t h e co de c is e n a b le d (t h e c o d e c is p o w e r e d d o w n b y defa u l t a f t e r p o w e r is f i rs t a p p lie d t o t h e ad1803). w h enev er t h e co dec is enab le d , t h e f r a m e ra te is swi t ch e d f r o m 8 kh z t o the p r o g r a m m e d co de c s a m p le ra t e , a n d w h ene v er t h e co de c is p o w e r e d do wn a g a in, t h e f r a m e ra te swi t ch es b ack to 8 kh z. w i t h th e b i t c lo c k al wa ys f i xed a t 4. 096 mh z, t h is g i v e s r i s e t o a f i rst ca us e o f va r i a t io n i n t h e n u m b e r o f b i ts b e tw e e n st a r ts o f da t a f r a m es. a s e cond ca us e o f a va r y in g n u m b er o f b i ts b etwe en s t a r ts o f da t a fr a m es is t h e p r es e n ce o f a s u b t le ji t t er i n t h e as s er - t i o n o f f r a m e sy n c w h e n t h e co de c is ena b le d . on a v er a g e , t h e r e is a n ex ac t m a tch b e t w e e n t h e pr o g r a mm e d s a m p le r a te a nd t h e f r a m e ra t e ; t h e f r a m e sy n c i t s e lf va r i es u p t o 4% o f a s a m p le p er i o d f r o m t h e ide a l a s s er t io n p o in t i n t i m e . f r a m e t ype s: syn c w h en t h e s e r i al in t e r f ace is i n ds p m o de , i t is p o s si b le t o acce s s on ly t h e upp e r or l o we r 8 - bit by te of a 1 6 - bit c on t ro l re g i ste r at a tim e . w h ile thi s i s s u f f i ci e n t f o r m a n i p u la tin g m a n y o f t h e ad1803 f e a t ur es, s o me f e a t ur es r e q u ir e m o r e t h a n eig h t con t rol b i ts and sp an m u l t i p le 8-b i t b y tes a nd/o r m u l t i p le 16-b i t w o r d s . t o al lo w al l b i ts o f a fe a t ur e t o t a k e ef fe c t sim u l t a n e o us l y , wr i t es t o cer t a i n co n t r o l b y t es o f cer t a i n r eg i st ers a r e ac t u al l y he ld in h o ldin g l a t c h e s un til a p a r t ic u lar co n t r o l b y t e o f th e f e a t ur e is w r itte n . n ote t h a t a re a d of a c o n t ro l re g i ste r a l w a y s re tu r n s t h e co n t e n ts o f a h o ldin g la t c h (if p r es en t f o r tha t r e g i s t er), which do es n o t n e ces s a r i l y r e f le c t t h e co n t r o l s e t t in g c u r r en t l y b e i n g us ed b y th e ad1 803. th e o n l y f e a t ur e tha t in co r p o r a t es this co m- plica t ion is t h e co de c s a m p le ra t e , w h ich wr i t es t o t h e lo w er b y te o f reg i s t er 0x40 a nd do es n o t t a k e ef fe c t un t i l t h e up p er b y t e of reg i st er 0x40 is wr i t t e n. o u t p u t f r o m ad1803 ( e i g ht z e ro s , f o l l o w e d b y e i g h t bi t s o f re g i s t e r re ad da t a add re s s e d b y th is fr a m e ) f re q u e ncy : 8khz w he n c o de c di s a bl e d, a nd e q ual t o s am p l e rat e w h e n co de c e nabl e d f r e q u e ncy : 4. 09 6m hz i n p u t t o ad180 3 ( 1 5 t rans m i t s a m p l e dat a bi t s , p l us c o n t ro l f ram e re q u e s t bi t ) o u t p u t f r o m ad1803 ( 16 cap t ure s a m p l e dat a bi t s ) i n p u t t o ad180 3 ( r e a d / w r i t e , ad dre s s , and by t e s e l e ct , f o l l o w e d by e i g h t bi t s o f r eg i st er w r i t e d a t a ) c15 c 14 c13 c 1 2 c11 c 10 c9 c8 c7 c6 c5 c4 c3 c 2 c1 c0 t 1 5 t1 4 t1 3 t 1 2 t1 1 t1 0 t9 t 8 t7 t6 t 5 t4 t3 t 2 t 1 c r rw a6 a5 a 4 a3 a2 a 1 b w 7 w 6 w 5 w 4 w 3 w 2 w 1 w 0 r7 r6 r5 r4 r3 r 2 r1 r0 bi t _ c l k da t a f ram e ( 1 6 bi t s ) : sd a t a _ o u t sd a t a _ i n c on tr ol f r a m e ( 1 6 b i t s ) : sd a t a _ o u t sd a t a _ i n 02 56 2- 0 11 figure 11. f r ame t y pes f ra m e i ns e rt e d i f re q ue s t e d b y cr bi t f ram e o rde ri ng : sy n c dat a f ram e co nt ro l f ra m e dat a f ra m e t 1 5: 1, c r rw , a6: 1 ,
b, w 7 : 0
i g no re d i g no re d t1 5 : 1 , c r s d at a_o u t r7: 0 c15: 0 c 15: 0 0 25 62 - 0 12 s d at a_i n p e r i o d e q ual s 1 / 8khz w he n co de c i s di s abl e d and p ro g ram m e d s a m p l e p e ri o d w he n co de c i s e n abl e d f i g u r e 12 . fr am e or d e ri n g rev. a | page 13 of 32
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register banks reg i st er addr ess es a r e b a s e d o n t h e i n t e l a c '97 s p e c if ic a t ion. b e ca us e t h e a c '97 sp e c if ica t ion lacks suf f i cien t vendo r def i n e d r e g i s t er s p ace t o co n t r o l al l ext e n d e d f e a t ur es o f th e ad1803, s o me c o n t rol re g i ste r s m u st b e ac c e ss e d i ndire c t ly u s ing re g i ste r ba nks. s e e th e b n k1 a n d b n k0 b i ts in reg i s t er 0 x 5c f o r deta ils. register access restrictions n e a r l y al l co n t rol r e g i s t ers ca n be r e ad f r o m o r wr i t t e n t o a t an y t i me. b e l o w is a list o f re str i c t ions t h a t m u st b e fol lo w e d to e n s u r e prop e r op e r a t i o n of t h e a d 1 8 0 3 : ? the c lo c k f r eq u e n c y de l i v e r e d to th e ad1803 on xt ali m u s t b e i d en t i f i e d (v i a a wr i t e to t h e x t al1 b i t a nd xt al0 b i t in reg i s t er 0x5c) bef o r e th e co dec is ena b led (via a wr i t e o f 0 t o b i ts d p dn o r ap d n in reg i s t er 0x3e). ? dur i n g ad c cal i b r a t io n, co dec sa m p le ra t e (reg i s t e r 0x4 0), a nd ad c s o ur c e a nd ga i n le vel m u st n o t b e chan ge d . c a li - b r a t ion is ini t ia ted each tim e the ad1803 s ad c is ena b le d ( s e e bi t ap d n i n reg i s t er 0x3e) a n d w h ene v er a 1 is wr i t t e n t o b i t ad cal in reg i s t er 0x5c . c o m p let i o n o f cal i b r a t io n is det er m i n e d b y p o l l in g t h e a d cal b i t. general-purpose i/o pin opera t ion ref e r t o reg i s t ers 0x4c thr o ug h 0x54 a nd reg i s t er 0x60 f o r co m p let e deta ils (s ee f i gur e 13). table 8. voice features f e a t ure p o w e r supply m a ximum sampling f r e q uenc y diff er en tial handset o utput single -ended line o utput o utput f u ll-scale r a nge o utput a t tenua t ion steps i npu t line/m ic m u x i n put f u ll-s c ale r a nge i n put 0 db/20 db g a in block pga , 0 db to 22. 5 db r a nge single -ended i n put diff er en tial i n put i n put r e sistance ad18 03 3 v to 5 v 16 kh z no y e s , 600 load 2.2 v p - p +12 db to ?34.5 db y e s 0.777 v r m s , 2.2 v p -p y e s y e s y e s no 10 k min var ie s with gain (see t a ble 9) table 9. i nput resistance vs. gain setting pga g ain ( d b) 20 db ga i n bl ock p g a ga i n (d b) r in (k) 0.0 to 22.5 disabled 0.0 to 22.5 100 0.0 to 22.5 enabled 20.0 to 42.5 10 rev. a | page 14 of 32
ad1803
control register map
co nf i g ( r e g . 0x4c[ n ] ) 0 = o u t p ut 1 = i n p u t s r q t r i g g e re d by "0" w r i t e t o : s t a t us ( r e g . 0x54[ n ] ) s t i c k y ( r e g . 0 x50[ n ] ) 1 0 s t i cky ( r e g . 0x50[ n ] ) 0 = no ns t i c ky i n p u t 1 = s t i cky i n p u t a c ' 97 m o de s l o t 12, o r g p i o s t at us ( r e g . 0 x54[ n ] ) w ake e nabl e ( r e g . 0x 52[ n ] ) o t he r i nt e rrup t s o urc e s i nt e rru p t we a k m o s dv d d g[ n ] p in po l a r i t y ( r eg . 0 x 4 e [ n ] ) 0 = c m o s 1 = o p e n d rai ns g [ n ] o ut p ut dat a ac' 97 m o de s : f r o m ac- l i nk s l o t 1 2 ds p m o de : f r o m re g . 0x54 p o l a r i t y ( r e g . 0x4e [ n ] ) 0 = act i v e hi g h 1 = act i v e l o w fig u re 1 3 . c o nc ept u al di ag r a m of g p i o pi n be hav i or table 10. register summary (direct mappe d registers) table 11. register summary (i ndi rect ma pp e d regi s t ers ) 0 25 62 - 0 13 a ddr ess regist er name a ddr ess regist er name 0x3c ex t e nded m o de m id 0x60 bank 1 gpio i n itial sta t e s 0x3e ex tended ad18 03 sta tus and c o n t r o l 0x64 bank 1 clock pad c o n t r o l 0x40 line d a c/adc s a mple r a t e c o ntr o l 0x60 bank 1monitor output c o n t r o l 0x46 ad1803 d a c/a d c l ev el c o n t r o l 0x4c gpio p i n c o nfigur a t ion 0x4e gpio p in p o lar it y /t ype 0x50 gpio p i n stick y 0x52 gpio p in w a ke -up m a sk 0x54 gpio p i n sta tus 0x56 m isc ella neous m o d em afe sta tus and c o n t r o l 0x5c c o nfigur a t ion 1 0x5e c o nfigur a t ion 2 0x7a v e rsion id 0x7c v e ndor id1 0x7e v e ndor id2 rev. a | page 15 of 32
ad1803
table 12. register map adr/b n k de fa ult d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0x 3c 0x x 00 x id1 id0 0 0 0 0 0 0 0 0 0 0 0 0 0 lin 1 0x 3e 0x f f 0 0 res res res res dp dn ap dn vp dn gpdn 0 0 0 0 dst a ast a vst a gst a 0x 40 0x 3e80 srg1 srg0 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 0x 46 0x 8080 dam 0 0 dal4 dal3 dal2 dal1 dal0 adm 0 ads adg20 adl3 adl2 adl1 adl0 0x 4c 0x 00ff 0 0 0 0 0 0 0 0 gc7 gc6 gc5 gc4 gc3 gc2 gc1 gc0 0x 4e 0x 00ff 0 0 0 0 0 0 0 0 gp 7 gp 6 gp 5 gp 4 gp 3 gp 2 gp 1 gp 0 0x 50 0x 0000 0 0 0 0 0 0 0 0 gs7 gs6 gs5 gs4 gs3 gs2 gs1 gs0 0x 52 0x 0000 0 0 0 0 0 0 0 0 gw 7 gw6 gw5 gw4 gw 3 gw2 gw1 gw0 0x 54 0x 00ff 0 0 0 0 0 0 0 0 gi 7 gi6 gi5 gi4 gi3 gi2 gi1 gi0 0x 56 0x 0000 0 0 0 mln k 0 0 0 0 0 0 0 0 0 l1b2 l1b1 l1b0 0x 5c 0x 18c0 res bn k1 bn k0 r34pm x t al1 x t al0 acsel adcal clked clkea res res res res res res 0x 5e 0x 0018 gpbar gpwak gpmon gpmic spchn spgbp spdss spis o spdl1 spdl0 res re s res res res res 0x 60/ 1 0x 0000 0 0 0 0 0 0 0 0 gpiv7 gp iv6 gpiv5 gpiv4 gpiv3 gpiv2 gpiv1 gpiv0 0x 64/ 1 0x 0077 0 0 0 0 0 0 0 0 res res res res x t lp cos2 cos1 cos0 0x 60/ 2 0x 4000 mmd1 mmd0 mdm mdl4 mdl3 mdl2 mdl1 mdl0 res res mam mal4 mal3 mal2 mal1 mal0 0x 7a 0x 0002 0 0 0 0 0 0 0 0 ver7 ver6 ver5 ver4 ver3 ver2 ver1 ver0 0x 7c 0x 4144 0 1 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0x 7e 0x 5380 0 1 0 1 0 0 1 1 1 0 0 0 0 0 0 0 rev. a | page 16 of 32
ad1803 rev. a | page 17 of 32 control register details extended modem id register address d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x3c id1 id0 0 0 0 0 0 0 0 0 0 0 0 0 0 lin1 0xx00x a write to this register has no effect on the states of bits within this register, but does trigger register 0x3e and bank 2 re gister 0x60 to be cleared to their default states, powering down the ad1803s codec resources. bit name description id1, id0 interface identification. these bits can be read to determine the ad1803s serial interface mode of operation. serial interface mode is chosen by the states of pin 13 and pin 12 when reset is deasserted (reset pin driven from low to high) for the first time after power is applied to the ad1803. 00 = ac link primary (mode chosen if pin 12 is high and pin 13 is high on first deassertion of reset ). 01 = ac link secondary (mode chosen if pin 12 is high and pin 13 is low on first deassertion of reset ). 10 = ac link secondary (mode chosen if pin 12 is low and pin 13 is high on first deassertion of reset ). 11 = dsp link (mode chosen if pin 12 is low and pin 13 is low on first deassertion of reset ). lin1 modem line 1 supported. for ac '97 compatibility, this bit retur ns a 1 when read to indicate that the ad1803 supports ac '97 modem line 1 features. extended status an d control register address d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x3e res 1 res 1 res 1 res 1 dpdn apdn vpdn gpdn 0 0 0 0 dsta asta vsta gsta 0xff00 1 res = reserved bit. to ensure future compatibility, reserved bits should be set to 0 when written and ignored when read. this register is forced to its default when power is first applied to the ad1803, the reset pin is driven low, or register 0x3c is written with any value. bit name description dpdn dac power-down. when this bit is set to 1 (default), all dac re sources within the ad1803 are powered down, and all dac data sen t over the serial interface is ignored. when this bit is set to 0, the digital dac resources are powered up. the analog dac resou rces are powered up only if the voltage reference of the ad1803 is powered up (bit vpdn in this register is set to 0), and the analog co dec of the ad1803 is selected as the partner to the digital codec of the part (bit acsel in register 0x5c is set to 0). 0 = enable digital dac resources; conditionally enable analog dac resources. 1 = power-down all ad1803 dac resources (default). apdn adc power-down. when this bit is set to 1 (default), all adc resources within the ad1803 are powered down, and all adc data-wor ds sent out of the ad1803 over the serial interface are midscale (zer o) and tagged invalid if the serial interface is configured i n an ac '97 mode. when this bit is set to 0, the digital adc resources wi thin the ad1803 are powered up. the analog adc resources within th e ad1803 are powered up only if both the voltage of the ad1803 referenc e is powered up (bit vpdn in this register is set to 0), a nd the analog codec of the ad1803 is selected as the partner to the digita l codec of the part (bit acsel in register 0x5c is set to 0) . each time the analog codec is powered up, an adc dc offset calibratio n is automatically initiated. this calibration requires approxi mately 104 sample periods (defined by register 0x40). it cannot be starte d until after the voltage reference is powered up (set bit vp dn in this register to 0), which requires about 48 ms. bit vsta in th is register can be polled first to determine if the voltage refe rence is powered up and then bit adcal in register 0x5c can be polled to determine if calibration is complete. during calibration, codec sample rate, adc source, and adc gain level must not be changed. 0 = enable ad1803 digital adc resources; conditionally enable ad1803 analog adc resources. 1 = power-down all ad1803 adc resources (default). vpdn voltage reference power-down. writes to this bit initiate codec voltage reference power-up and power-down sequences. bit vsta i n this register can be polled to monitor current voltage referenc e status. until the voltage reference is powered up, the analog adc and dac channels of the ad1803 ignore the settings of bit apdn and bit dpdn and the part remains powered down. 0 = enable voltage reference. 1 = power-down voltage reference (default).
ad1803
bit name description gpdn gpio p o w e r -d o wn. s e tting this bit aff e c t s the beha vior of the ad 1803 only whe n it is c o nfigur e d in an a c '97 m o de (see r e g i ster 0x3c ) . this bit deter mines whet her the logic le vels r e c ei v ed on the genera l-pur p ose input/outpu t ( g pio ) pins ar e r eflec ted on t he bits in slot 12 of the a c '97 link , and whether or not the sta t es of bits in slot 12 deter mine the lo gic lev e ls to dr iv e out of gpio pi ns tha t ar e c o nfigur ed as outputs . see bit spgbp in r e g i st er 0x 5e f o r mappi n g . c o n t r a r y to the a c '97 specific a t ion , the setting o f t h is bit does not ac tually c o n t r o l the pow er -up/pow e r - d o w n sta t e of the gpio pins . ad 1803 gpio pins ar e pow e r ed up and per f or m the func tions they ar e assigned b y pr ogr a mming r egister 0x4c thr o ugh r egister 0x54 and r egister 0x5e. 0 = slot 12 output bits r e flec t log i c lev e ls r e c e iv ed on gpio pi ns . slot 12 input bits deter mine logic bev e ls to dr iv e out gpio pins c o nfigur ed as outputs . 1 = slot 12 output bits all 0 (def a ult) . slot 12 input bits ar e ig nor e d . dst a d a c sta tus . this bit exists solely f o r a c '97 c o mpa t ibilit y . i t s pur p ose is to p r o vide a handsha k e f o r d a c po w er-up /pow er- d o w n st a tus changes i n itia te d b y wr ites to bit dpdn in this r eg ister . beca use the ad1803 r e sponds to a wr ite of bit dpdn bef o r e it is possi ble to r ead this bit in a f o llo w ing ser ial in ter f ac e frame , ther e is no r e ason t o poll this status bit. w r ites to this bit ha v e no eff ec t on ad180 3 beha vio r . ast a adc sta tus . this bit exists solely f o r a c '97 c o mpa t ibilit y . i t s pur p ose is to p r o vide a handsha k e f o r adc po w er-up /pow er- d o w n st a tus changes i n itia te d b y wr ites to bit apdn in this r eg ister . beca use the ad1803 r e sponds to a wr ite of bit apdn pr io r to it being pos sible t o r e ad this bit in a f o llowing serial in t e r f ac e fr ame , ther e is no r e ason t o poll this sta tus bi t. w r it es t o this bit ha v e no eff e c t on ad1803 beha vior . vst a v o ltage r e f e r e nc e sta tus . this bi t can be polled to monitor the st a tus of the c o dec v o ltage r e f e r e nc e of the ad1803. w h en r e ad as a 0, the v o ltage r e f e r e nc e i s pow e r ed do wn or in the pr o c ess of pow er ing up . whe n r e ad as a 1, th e v o ltage r e f e r e nc e is pow e r ed u p or in the pr o c ess of po w er ing do w n . ap pr o x im a t el y 48 ms af ter bit vpdn in this r e g i st er is set t o a 0, this bit tr ansitions fr om a 0 to a 1 indica ting tha t the v o ltage r e f e r e nc e is fully pow er ed up . appr o x ima t ely 0.8 ms af t e r vpd n is set t o a 1, this bit tr ansitions fr om a 1 t o a 0 ind ica ting tha t the v o ltage r e f e r e nc e i s fully po w e r e d - d o wn. i f a clock is dr iv e n on to the x t ali pin (ra t her tha n genera ted by a cr ystal pla c ed bet w ee n the x t ali pin and x t al o pin), and it is de sir e d to stop this clo ck f o r ad d i tional system p o w e r sa ving s , stop the clock af ter this bit falls to 0. w r it es to this bi t ha v e no eff e c t on the beha vior of the ad1803. gst a gpio sta tus . t h is bit ex ists solely f o r a c '97 c o mpa t ibi l it y . i t s pur pose i s to pr ovi d e a handshake f o r d a c po w e r- up/pow er- d o w n sta tus change s initia ted b y wr ites to bit gpdn in this r e g ist er . how e v e r , sinc e the ad1803 r e sponds to a wr ite of bit gpdn pr io r t o it being po ssib l e to r ead this bit in a f o llowing ser i al in ter f ac e fr ame , ther e is no r e ason t o poll this sta tus bit. w r it es t o th is bit ha v e no eff e c t on the beha vior of the ad1803. line dac/adc sam p le rate control register
a ddress d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 defau lt 0x40 srg1 srg0 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 0x3e80 this r e g i s t er is fo r c ed t o i t s defa u l t o n l y w h en p o w e r is f i rs t a p plied t o t h e ad1 803. do n o t wr i t e t o this r e g i st er while a n a d c ca l i b r a t io n is i n p r og r e s s (s ee b i t ap dn in reg i s t er 0x3e a nd b i t ad cal in reg i s t er 0x5c). w h en t h e ad1 803 s e r i al in t e r f ace is co nf igur ed in ds p m o de , wr i t es t o t h e lo w e r b y t e o f this r e g i s t er a r e t e m p o r a r il y p laced in a h o ld in g r e gi s t e r a n d d o n o t a c t u all y tak e e f f e ct un til t h e u p pe r b y t e i s wri t t e n . t h i s e n sur e s th a t t h e 16- b i t sa m p le ra t e o nl y tak e s e f f e c t as a w h ole. re ads o f t h e l o w e r b y t e o f t h is r e g i s t er r e t u r n t h e con t e n ts o f t h is h o ldin g r e g i s t er t h a t do n o t n e cess a r i l y r e f lec t t h e c u r r e nt s a mp l e r at e . bit name description srg1, srg0 sample r a te granular it y . these bits sele c t the lsb w eig h t ing of the bits sr[13:0] (sample r a te s elec t ). these bits selec t a fundamen tal lsb w e ig h t ing of either 1 h z , 8/7 h z , or 10/7 h z f o r bits sr[13:0]. 00 = sr[13:0] ls b w e ig h t is 1 h z . 01 = sr[13:0] ls b w e ig h t is 8/7 h z . 10 = sr[13:0] ls b w e ig h t is 10/7 h z . 11 = r eser v ed . sr13 to sr0 sample r a te s e l e c t . bits srg[1:0] (sample r a te granular it y), th ese bits define the sample r a te f o r both the adc and d a c c o dec channe ls . p e r mitted settings of sr[13:0] r a nge fr om 6400 to 16000 when srg[1:0] = 00, 5600 to 14,000 when srg[1:0] = 01, and 4480 to 11,200 when srg[1:0] = 10. the defaul t sample ra te is 16,000 h z . rev. a | page 18 of 32
ad1803
dac/adc level control register
addr es s d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x46 dam 0 0 dal4 dal3 dal2 dal1 dal0 adm 0 ads adg 20 adl3 adl2 adl1 adl0 0x80 80 this r e g i s t er is fo r c ed t o i t s defa u l t o n l y w h en p o w e r is f i rs t a p plied t o t h e ad1 803. the s t a t es o f bi t ads, bi t ad g 20, a nd bi t adl3 t o bi t ad l0 in t h is reg i s t er m u s t n o t b e chan ge d w h i l e an ad c c a lib r a t io n is i n pro g re s s i f th e analog co de c o f th e ad180 3 is in us e (s e e b i t ap dn in reg i s t er 0x3e a nd b i t ad cal in reg i st er 0x5c). bit name description da m dac m u t e . 0 = d a c outpu t enabled . 1 = d a c outpu t mut e d ( f or c e d t o mids c al e) (defaul t). d al4 t o d a l0 d a c a t tenua t ion l e v e l s e le c t . l e ast sig n ifican t bit r e pr ese n ts ?1.5 db . this a t tenua t ion is v a lid when the ad1803 s analog c o dec is used with the dig i tal c o dec of th e ad18 03 (bit a cs el in r e g i ster 0x5c = 0). 00000 = +12.0 db gain (default). 11111 = ?34.5 db a t tenua t ion. adm adc mu t e . 0 = adc sample s pas s ed . 1 = adc sample s substituted with mid scale ( 0 ) d a ta ( d efault) . ads analog adc i n put s e lec t . the st a t e of this bit has no eff e c t on adc beha vior unless bit a csel in r e g i st er 0x5c is set t o 0 (default). this selec t s the analog c o dec of the ad1803 to par t ner wi th the dig ital c o dec of the par t . i f this bit is used to se lec t the mic input as the adc input of the ad1803, p i n 15 must first be assig n ed to ser v e as this mic input r a ther than its default r o le as a gpio pin. this is done by se tting bit gp mic in r e g i ster 0x5e to 1. 0 = p i n 16 (rx input) selec t ed as ad1803 adc in put sour c e (default). 1 = p i n 15 (mic i n put) selec t ed as ad1803 adc i n put so ur c e (r e q uir e s gp mic in r e g i ster 0x5e set to 1). adg20 ad1803 analog adc 20 db g a in enable . the st a t e of this bit has no eff e c t on adc beha vior unle ss bit a csel in reg ister 0x5c is set to 0 ( d efault). this selec t s the analog cod ec to par t ner with the dig i tal c o dec . t o tal adc gain is the summa tion due t o thi s bit and bit adl3 t o bit adl0. 0 = 0 db gain (d efaul t ). 1 = 20 db gain. adl3 t o adl0 ad1803 adc g a in l e v e l s e le c t . t h e sta t e of these bits has no eff e c t on adc beha vior unless bit a csel in r e g ister 0x5c is set to 0 (default). this selec t s the ad1 803 s analog c o dec to par t ner the ad1803 s dig ital c o dec . 0000 = 0.0 db g a in (default). 1111 = 22.5 db gain. rev. a | page 19 of 32
ad1803
gpio pin configuration registe r
a ddress d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 defau lt 0x4c 0 0 0 0 0 0 0 0 gc7 gc6 gc5 gc4 gc3 gc2 gc1 gc0 0x00ff this r e g i s t er is fo r c ed t o i t s defa u l t o n l y w h en p o w e r is f i rs t a p plied t o t h e ad1 803. bit name gc7 to gc2, gc0 gc1 description g ener a l-p u r pos e i/o p in c o nfig ur a t ion. these b its define the dir ec t ionalit y of g p io pins with c o r r espo nding numbers . b y default , all gpio pins ser v e as inputs , but wi th w e ak (~100 a with a 3.3 v supply , ~140 a with a 5.0 v supply) pull-up devic e s in ter n al to the ad1803 enable d . s ee r eg ister 0 x 4e to disable t h ese w eak pull- up d evic e s . note tha t gpio p i n 1 is alw a ys an input and cannot ser ve as an output. also , not e tha t bits in this r egi ster ar e igno r ed if the gpio pin they c o n t r o l h a s bee n assign ed to ser v e an alte rna t e specia l pur pose (see bits in r egister b y mor e tha n 0.3 v ) . gpio p i n 1 is sour c ed by the analog su p p ly ( p ins a v dd and a g nd ) . all other gpio pins ar e sour c e d b y the dig i tal supply (p in dvdd an d p i n dg nd ). 0 = gpio pin ser v es as an output. 1 = gpio pin ser v es as an input (default). gpio p in 1 is alw a ys an i n put (default=1) and c a nnot ser v e as an output. an y w r it es t o this r e gis t er will be ign o red . gpio pi n po larity/t yp e register
a ddress d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 defau lt 0x4e 0 0 0 0 0 0 0 0 gp7 gp6 gp5 gp4 gp3 gp2 gp1 gp0 0x00ff this r e g i s t er is fo r c ed t o i t s defa u l t o n l y w h en p o w e r is f i rs t a p plied t o t h e ad1 803. bit name description gp7 to gp0 gpio i n put p o larit y / o utput d r iv er t y pe selec t . t h ese bits con t r o l gpio pins with c o r r esponding numbers . the ef f e c t they ha v e is dependen t on g p io pin dir ec t io nalit y (see r egister 0x4c ). when a gpio pin ser v es as an input, th ese bits se lec t the logic lev e l nec e ssar y t o set a stick y sta tus bit which is used t o trigger an in t e rrupt (see r e g i sters 0x50 and 0x52). w h en ser vi n g as an in put, these bits deter mine whether a w ea k pull-up r e c eiv e s a low , the w e ak pull-up is disabled . i f an input is set t o ac tiv e low , and ther ef or e nomin ally r e c eiv es a hi gh, the w eak pull-up is en able d . m ean whil e , whe n a gpio pin se r v es as an output, these bits deter mine whether a cmos or o p en dr ain with w e a k pull-up dr iv er is ac ti v a ted . i f a gpio pin is d e fined as an input (c orr e spon ding gc bit in r e g i st er 0x4c is set t o 1) 0 = i n put is ac tiv e high, w e ak pul l -up disable d .
1 = i n put is ac tiv e lo w , w e ak pull-up enabled (default).
i f a gpio pin is defined as an output (c or r e spon d i ng gc bit in r e g i st er 0x4c is set t o 0).
0 = o utput d r iv er is cmos.
1 = o utput d r iv er is open dr ain with w e ak pull-up enabled (default).
gpio s t ic ky pi n regis t er
a ddress d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 defau lt 0x50 0 0 0 0 0 0 0 0 gs7 gs6 gs5 gs4 gs3 gs2 gs1 gs0 0x0000 this r e g i s t er is fo r c ed t o i t s defa u l t o n l y w h en p o w e r is f i rs t a p plied t o t h e ad1 803. bit name description gs7 to gs0 gpio stick y c o ntr o l . these bits con t r o l gpio pins with c o rr es pon ding numbers . they deter mine whether a r e ad of r egister 0x54 r etur ns either the cur r en t logic l ev el r ec ei v ed on a gpio pin, or a stick y sta tus bit which ind ic a tes if a selec t ed logi c lev e l (see r egister 0x4e) h a s been r ec ei v e d sinc e this stick y sta tus bit w a s last clear e d . stick y sta tus bits ar e clea r ed b y wr ites to the ir asso cia t ed c o n t rol bits in r egiste r 0x54, and whe n ev er the cur r e n t gpio pin r ec e iv ed logic l ev e l i s selec t ed as the r egister 0x 54 r e turn v a lue . 0 = r ead s of r e gister 0x54 r etur n cur r en t sta t e o f gpio pin, stick y sta tus bit cleared ( d efault) . 1 = r ead s of r e gister 0x54 r etur n a stick y sta tus bit set b y gpio pin le v el s elec t e d b y r egister 0x4e. rev. a | page 20 of 32
ad1803 rev. a | page 21 of 32 gpio pin wake-up mask address d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x52 0 0 0 0 0 0 0 0 gw7 gw6 gw5 gw4 gw3 gw2 gw1 gw0 0x0000 this register is forced to its default only when power is first applied to the ad1803. bit name description gw7 to gw0 gpio wake-up mask control. a gpio pin triggers an interrupt prov iding that it is enabled to cause interrupts by the correspondi ng numbered bit in this register, and it has its associated sticky status bit set. for the associated sticky status bit to be set, the gpio input must first be enabled to be sticky by the gs bit in regist er 0x50, and then the logic level selected by a gp bit in regis ter 0x4e must be received on the associated gpio pi n. when an interrupt is triggered, pin 12 is driven high providing pin 12 is enabled to serve as an interrupt output (see gpwak bit in register 0x5e). if the ad1803s serial interface is configured in an ac '97 mode , interrupts are also reflected on bit 0 of slot 12 of each frame, even if pin 12 is not enabled to respond to an interrupt. also in ac '97 mode, if reset is asserted when an interrupt is triggered, the sdata_in pin is dr iven from low (default during reset ) to high to wake an ac '97 controller. refer to the ac '97 specification fo r complete details. activated gp io pins can trigger interrupts. the source of the interrupt can be determined by reading register 0x54. 0 = gpio pin disabled from ca using interrupts (default). 1 = gpio pin enabled to cause in terrupts (providing co rresponding gs bit in register 0x50 = 1). gpio pin status register address d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x54 0 0 0 0 0 0 0 0 gi7 gi6 gi5 gi4 gi3 gi2 gi1 gi0 0x00ff this register is forced to its default only when power is first applied to the ad1803. bit name description gi7 to gi0 gpio status. each bit corresponds with a gpio pin of the same nu mber. when a bit is read, it reflects either the current logic level received on a gpio pin or the state of the sticky status bit that is set if a selected logic level has been received on a gpio pin since the last time the sticky status bit was cleared (see register 0x 4e, register 0x50, and register 0x52). when a bit is written wi th a 0, the associated sticky status bit is cleared. no te that it is not necessary to write a 1 to a bit after writing a 0 since it is the act of writing a 0 to a bit itself that clears the sticky status bit. when a bit is written with a 1, the associated sticky status bit is unaffect ed. if the ad1803s serial interface is configured in dsp mode (see register 0x3c), writes to this register also control the logic level d riven out on the gpio pins provided that a gpio pin is configured as an output (see register 0x4c) and is serving as a gpio pin (see register 0x5e). if the ad1803s serial interface is configured in an ac '97 mode, gpio output states are determined by the bits in ac link slot 12 rather than writes to this re gister (see bit spgbp in register 0x5e an d the ac '97 specification for further detai ls). miscellaneous modem afe stat us and control register address d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x56 0 0 0 mlnk 0 0 0 0 0 0 0 0 0 lib2 lib1 lib0 0x0000 this register is forced to its default only when power is first applied to the ad1803. bit name description mlnk ac link disable. this bit has no effect on the behavior of th e ad1803 unless it is configured as an ac '97 primary device (see register 0x3c). when this is the case, writing a 1 to this bit puts the ac '97 link interface in to a sleep mode by causing the ad1803 to drive the bit_clk pin low within one bit_clk period after the completion of slot 2 (the slot in which writes to control regi sters occur). while in this sleep mode, an ac '97 controller can wake the ad1803 interface either by pulsing the sync pin, or by asserting and then deasserting the reset pin. refer to the ac '97 specification for comp lete details. note that the interface is put to sleep, regardless of interface mode, if the reset pin is asserted. lib2 to lib0 loopback modes. 000 = no loopback. normal signal pathways engaged (default). 001 = analog loopback. analog adc output to analog da c input (at analog interface to digital codec). 010 = local loopback. dac output to adc input (at analog pins). 011 = digital loopback. digital dac output to digital adc input (at digital interface to analog codec). 1xx = no loopback. normal signal pathways engaged.
ad1803 rev. a | page 22 of 32 configuration 1 register address d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x5c res 1 bnk1 bnk0 r34pm xtal1 xtal 0 acsel adcal clked clkea res 1 res 1 res 1 res 1 res 1 res 1 0x18c0 1 res = reserved bit. to ensure future compatibility, reserved bits should be set to 0 when written and ignored when read. this register is forced to its default only when power is first applied to the ad1803. bit name description bnk1, bnk0 register bank select. since the ac '97 specification lacks sufficient vendor specified register space to control all extended features of the ad1803, some control registers must be accessed indirectly using register banks selected by these bits. 00 = reserved. 01 = bank 1: ad1803 i/o control registers. 10 = bank 2: ad1803 codec control registers. 11 = reserved. r34pm reset power mode select. when this bit is set to 0, th e ad1803 is completely powered down whenever the reset pin is asserted (driven low). this bit overrides the settings of all other power control bits. when this bit is set to 1, various feat ures of the ad1803 remains powered up during reset as individually enabled by their relate d control bits (see other bits in this register) 0 = during reset , power down the ad1803. 1 = during reset , allow enabled features to remain powered up (default). xtal1, xtal0 clock identification. with the exception of the serial interface, which is always clocked by the bit_clk pin, these bits identi fy the clock source and frequency to be used by all other resources wi thin the ad1803. the default settin g of these bits is dependent on the chosen ad1803 serial interface configuration (see register 0x3c). there are three reasons why it might be desirable to alter from the default setting: if the bit_clk is the default clock source, but the bit_clk has ex cessive edge noise that interferes with codec performance, th an a crystal or other clean clock source could be taken from the xtali pin instead. if the bit_clk is the default clock source, but the bit_clk is st opped during a period of time when ad1803 functionality is sti ll necessary, such as ring validation and wake-up signaling during d3-cold, then the clock source could be switched to the xtali pin while the bit_clk is suspended. if the xtali is the default clock source and the default crystal frequency is not the one actually used, the correct crystal frequency must be identified prior to the adc, dac, or barrier interface being enabled (see register 0x3e). also note that if the ad1803 is the master of bit_clk (serial interface in ac '97 primary mode or dsp mode), bit_clk cannot be at its proper frequency until the ad1803 is informed what clock frequency it is receiving. until then, the bit_clk frequency is off by the ration of the actual to the default assumed frequency. as a final caution, if the clock freque ncy is chosen to be 32.768 mhz (setting 01 of these bits), and the ad1803 is chosen to be an ac '97 primary device , the ad1803 is incapable of producing the ac '97 specified 12.288 mhz bit_clk because there is no integer divisor between these frequencies. in this situation, the ad1803 violates the ac '97 specification and outputs a 16.384 mhz bit_clk. 00 = 12.288 mhz from bit_clk (default if in an ac '97 secondary mode). 01 = 32.768 mhz from xtali. 10 = 24.576 mhz from xtali (default if in either ac '97 primary mode or dsp mode). 11 = 12.288 mhz from xtali. acsel analog codec select. this bit selects the analog codec that is used in conjunction with the digital codec of the ad1803. 0 = ad1803 analog codec selected (default). 1 = reserved. adcal adc calibration/recalibration. writing a 1 to this bit initiates a dc offset calibration of the codecs adc channel, which requ ires approximately 104 sample periods (defined by register 0x40). ad c calibration is automatic each time the analog adc of the ad1803 is enabled. when this bit is read, a 1 is returned if cali bration is in progress and a 0 is returned when calibration is completed or not in progress. during calibration, the adc retur ns midscale (zero) samples. during calibration, codec sample rate, adc source, and adc gain must not be changed. clked clk_out enable while reset is deasserted (driven high). this bit controls the operation of the clk_out pin while the reset pin is deasserted. see bit clkea for clk_out operation while reset is asserted. each time reset is deasserted (driven from low to high), this bit is automatically set to 1 to ensure that a clock is always available to hardware outside the ad1803 after a reset . if this clock is not needed, this bit should be set to 0 by software after each reset for optimal power savings. 0 = when reset is deasserted, clk_out is driven low. 1 = when reset is deasserted, clk_out reflects clock on xtali (default after deassertion of reset ).
ad1803 rev. a | page 23 of 32 bit name description clkea clk_out enable while reset is asserted (driven low). this bit controls the operation of the clk_out pin while the reset pin is asserted. see bit clked for clk_out operation while reset is deasserted. if bit r34pm is se t to 0, this bit is ignored, and clk_out is driven low while reset is asserted. 0 = when reset is asserted, clk_out is driven low. 1 = when reset is asserted, clk_out reflects clock received on xtali (providing r34pm set to 1) (default). configuration 2 register address d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x5e gpbar gpwak gpmon gpmic spchn spgbp spdss spiso spdl1 spdl0 res 1 res 1 res 1 res 1 res 1 res 1 0x0018 1 res = reserved bit. to ensure future compatibility, reserved bits should be set to 0 when written and ignored when read. this register is forced to its default only when power is first applied to the ad1803. bit name description gpbar gpio interface select. 0 = use ad1803 pin 24, pin 23, and pin 22 as g[5], g[6], and g[7] respectively (default). 1 = reserved. gpwak g[3]/wake interrupt signal select. 0 = use ad1803 pin 12 as gpio[3] (default). 1 = use ad1803 pin 12 as wake interrupt (see register 0x52). gpmon gp[4]/monitor output select. 0 = use ad1803 pin 11 as gpio[4] (default). 1 = use ad1803 pin 11 as - monitor output (see register 0x60 bank 2). gpmic gp[1]/mic input select. 0 = use ad1803 pin 15 as g[1] (default). 1 = use ad1803 pin 15 as analog mic in put (see bit ads in register 0x46). spchn serial port chaining mode enabled. this bit is ignore d unless the ad1803 is in an ac '97 serial interface mode (see register 0x3c). this bit can be used to chain multiple ac '97 devices to a single 4-wire ac '97 link. consult analog devices, inc. for further details. 0 = adi chaining mode disabled (default). 1 = adi chaining mode enabled. spgbp serial port gpio bit placement select. this bit is ignore d unless the ad1803 is configured in an ac '97 serial interface mode (see register 0x3c). writes to this bit take effect on the current serial interface frame. 0 = state of ad1803 g[7] through g[0]0 reflec ted on bits [1:4] of slot 12 (default). 1 = state of ad1803 g[7] through g[0] reflected on bits [19:12] of slot 12 spdss serial port data slot size select. this bit is ignored unless the ad1803 is configured in an ac '97 serial interface mode (see register 0x3c). when set to 1, the four lsbs of all 20-bit data slots ar e dropped, allowing a simpler connection with a dsp. writes to t his bit take effect during the current frame, but can distort the current frames slot alignment. as a result, when the state of this bi t is changed, all data slots sent to the ad1803 should be set to zero and all data slots received from the part should be ignored. 0 = data slots are 20 bits (default). 1 = data slots are 16 bits. spiso serial port isolate. when this bit is set to 1, the ad1803 serial interface is isolated from th e outside system whenever reset is asserted. this is achieved by ignoring the signals received on serial interface input pins an d driving serial interface output pins weakly (less than 200 a), rather than with nominal output drive strengths. this bit should be set to 1 prior to a controller o n the other side of the parts serial interface losing power if the ad1803 continues to receive power. it can also be set to 1 to sav e power if the parts serial interface input pins continue to make transitions while reset is asserted. spdl1, spdl0 serial port data slot location select. these bits are ignored un less the ad1803 is configured in an ac '97 serial interface mod e (see register 0x3c). writes to these bits take effect during the current frame, but data sent during the current frame can be distor ted or dropped. for reliable operation, these bits shou ld not be changed while the codec is enabled. 00 = ad1803 uses slot 5 to send and receive sample data (default). 01 = ad1803 uses slot 10 to send and receive sample data. 10 = ad1803 uses slot 11 to send and receive sample data. 11 = reserved.
ad1803 rev. a | page 24 of 32 bank 1gpio initial states register address d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x60 0 0 0 0 0 0 0 0 gpiv7 gpiv6 gpiv5 gpiv4 gpiv3 gpiv2 gpiv1 gpiv0 0x0000 this register is forced to its default only when power is first applied to the ad1803. bit name description gpiv7 to gpiv0 gpio pin initial value. when reset is deasserted for the first time after power is ap plied to the ad1803, the states of all gpio pins are sampled and stored in this register. writ es to this register and subsequent logic level changes on gpio pins have no effect on the values reported by reads of this register. while the sampled stat es of gpio pin 2 and pin 3 are used by the ad1803 to determine serial interface mode (see register 0x3c), all remaining gpio pins are av ailable for use, if beneficial, as identification bits to hos t software or hardware. immediately after power is first ap plied to the ad1803, all gpio pins by de fault serve as inputs, but with weak pull- up devices internal to the enabled ad1803. since these pull-up device s have an effective resistance of about 30 k, external resis tors of less than 8 k tied to digital ground (dgnd pin) must be used for logic lows to be sampled. bank 1clock pad control register address d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x64 0 0 0 0 0 0 0 0 res 1 res 1 res 1 res 1 xtlp cos2 cos1 cos0 0x0077 1 res = reserved bit. to ensure future compatibility, reserved bits should be set to 0 when written and ignored when read. this register is forced to its default only when power is first applied to the ad1803. bit name description xtlp crystal oscillator low power mode enable. depending on board desi gn and crystal used, this bit can be set to 1 to engage a crystal oscillator low power mode, which saves up to 0.7 ma. this mode reduces the amount of energy that an ad1803 provides to keep a crystal oscillating, but otherwise has no ef fect on ad1803 behavior. if a clock is driven onto the xtali pin from an external source, rather than generated by a crystal connected between the xtali pin and xtalo pin, the optimal setting for this bit is 1, although with only a slight power benefit. 0 = normal power mode (default). 1 = low power mode. cos2 to cos0 clk_out pin drive strength select. this bit can be used to redu ce em emissions, or three-state the clk_out pin. 000 = 0% of full drive strength (pad three-stated). 001 = 13% of full drive strength. 010 = 25% of full drive strength. 011 = 38% of full drive strength. 100 = 63% of full drive strength. 101 = 75% of full drive strength. 110 = 88% of full drive strength. 111 = 100% of full drive strength (default).
ad1803 rev. a | page 25 of 32 bank 2monitor output control register address d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d2 d2 d1 d0 default 0x62 mmd1 mmd0 mdm mdl4 mdl3 mdl2 mdl1 mdl0 res res mam ma l4 mal3 mal2 mal1 mal0 0x4000 this register is forced to its default only when power is first applied to the ad1803. bit name description mmd1, mmd0 monitor output mode. the monitor output of the ad1803 provides a programmable mix of the adc and dac signals passing through the codec of the part. pin 11 serves as the monitor output, providing bit gpmon in register 0x5e is set to 1. otherwise , pin 11 serves its default role as a gpio pin. when the monitor output is enabled (powered up) us ing bits mdm[1:0], the monitor output is in the form of digital - modula tor bit stream with a maximum edge rate (carrier) of 512 khz. one of two different - modulator types can be activated: either a first order that gene rates 6 db more signal swing th an the other choice but has more inband noise and idle tones or a third order that has half the signal swing but significantly superior inband noise and negligi ble idle tones. to extract the signal from the - modulator noise, it is recommended that the monitor output be filtered by connec ting pin 11 to a 1 k resistor in series with a parallel 4.7 k resi stor and 100 nf capacitor combination which is then tied to digi tal ground (dvdd pin). this filter, with the output ta ken from the middle node, has a 1500 hz corner to filter out high frequency - nois e. it generates an approximate 1 v p-p output when using a 5 v digital supply with the monitor output configured as a first order (mm d1 and mmd0 set to 10) if the filter output load is greater than or eq ual to 20 k. other filter networks can also be used, perhaps to save power or increase effective output signal swing, but for long term reliability, care must be taken to ensure that the monitor o utput never sources more than 5 ma. the recommend ed filter dissipates approximately 1 ma. 00 = reserved. 01 = monitor output powered down and driven low (default). 10 = monitor enabled, first-order - output, signal swing: 0% to 100% ones (b est signal amplitude). 11 = monitor enabled, third-order - output, signal swin g: 25% to 75% ones (best signal snr post filter). mdm monitor output dac mix mute. if both adc and dac mix are muted, the monitor output should be powered down (mdm[1:0] set to 10) to achieve a quieter mute. 0 = dac mix level determined by bits mdl4 to mdl0 (default). 1 = dac mix is muted. mdl4 to mdl0 monitor output dac mix level. unless muted by the mdm bit in this register, these bits control the amount of dac signal that is mixed into the monitor output. representation is twos complement with an lsb weighting of 3 db and a permissible range of +45 db to ?18 db. if the analog codec of the ad 1803 is in use (acsel set to 0), the dac si gnal mixed is taken before this attenuati on is applied. in either case, the dac signal mixed is always ta ken before the mute bit dam in register 0x46 is applied. 01111 = +45 db. 00000 = 0 db (default). 11010 = ?18 db. mam monitor output adc mix mute. if both adc and dac mix are mute d, the monitor output should probably be powered down (mam[1:0] set to 10) to achieve a quieter mute. 0 = adc mix level determined by bits mal[4:0] (default). 1 = adc mix is muted. mal4 to mal0 monitor output adc mix level. unless muted by the mam bit in this register, these bits control the amount of adc signal that is mixed into the monitor output. representation is twos compleme nt with an lsb weighting of 3 db and a permissible range of +45 db to ?18 db. the adc signal mixed is always taken after the gain specified by bit dal4 to bit dal0 in register 0x46 is app lied, but before the mute bit adm in register 0x46 is applied. 01111 = +45 db. 00000 = 0 db (default). 11010 = ?18 db. version id register address d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x7a 0 0 0 0 0 0 0 0 ver7 ver6 ver5 ver4 ver3 ver2 ver1 ver0 0x0002 bit name description ver7 to ver0 ad1803 version. writes to this register ha ve no effect. the latest version of the ad1803 is 0x0002.
ad1803
ven d or i d 1 register
a ddress d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 defau lt 0x7c 0 1 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0x4144 w r it es t o reg i s t e r 0 x 7c a n d reg i s t er 0x7 e ha v e n o ef f e c t . w h en r e a d , a ddr es s 0 x 7c a n d a ddr es s 0 x 7 e r e t u r n 0 x 4 144 a n d 0x53 80, r e s p e c t i vely , which, tak e n t o g e th er , ma p t o ads in ascii f o l l o w ed b y a d dr es s 0x 80. ads is r eg i st er e d i n t h e a c '97 sp e c if ica t io n t o i d en t i f y ana log de vices as t h e vendo r , a nd t h e f i nal b y t e o f a ddr es s 0x80 is us ed t o iden t i f y th e ad1803 (v en do r s e lec t e d val u e). ven d or i d 2 register a ddress d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 defau lt 0x7e 0 1 0 1 0 0 1 1 1 0 0 0 0 0 0 0 0x5380 rev. a | page 26 of 32
ad1803 rev. a | page 27 of 32 applications application circuits lm386 speaker modem datapump 3.3v core-vdd link-vdd bit_clk reset sync sdata_out sdata_in flag xtalo xtali g[4]/mout tx g1/mic g[0] g[5] rx ad1803 modem dvdd avdd reset bit_clk sync sdata_out sdata_in clk_out xtalo xtali 24.576mhz primary codec id = 00 3.3v aux 3.3v aux 3 .3 v aux g[6] g[7] g[2] g[3]wake oh ring cid 911_detect vcc t x ? oh t x + r x + r x ? ring cid litelink daa cpc5610 1 2 3 4 rj11 lmv331 02562-014 figure 14. pc/embedded modem g[4]/mout tx g1/mic g[0] g[5] rx ad1803 modem dvdd avdd reset bit_clk sync sdata_out sdata_in clk_out xtalo xtali 24.576mhz secondary codec id = 01 3.3v aux 3.3v aux 3.3v aux g[6] g[7] g[2] g[3]wake oh ring cid vcc t x ? oh tx+ rx+ r x ? ring cid litelink daa cpc5610 1 2 3 4 rj11 pc_beep reset bit_clk sync sdo sdi[0] sdi[1] line_out a d1881a audio codec dvdd avdd reset bit_clk sync sdata_out sdata_in xtalo xtali primary codec id = 00 pc_beep eapd/cin line_in cd_in mic cs1 cs0 phone_in 5v agnd to speaker_out jack from line_in jack from cd_in atapi connector from mic jack amr/ cnr/ acr connector 02562-015 figure 15. audio modem riser
ad1803 rev. a | page 28 of 32 g[4]/mout tx +? g1/mic g[0] g[5] rx ad1803 audio code dvdd avdd reset bit_clk sync sdata_out sdata_in clk_out xtalo xtali 24.576mhz 3.3v aux g[6] g[7] g[2] g[3]wake oh ring 1 2 3 4 rj11 mono phone reset bit_clk sync sdo sdi[0] primary codec id = 00 amr/ cnr/ acr connector 3.3v hybrid dc hold ring detect t1 relay 02562-016 figure 16. modem riser with discrete daa a d1803 codec dvdd avdd reset bit_clk sync sdata_out sdata_in g[2] g[3]/wake dsp mode clk_out xtalo xtali adsp-218x clkin fl1 sclk tfs rfs dt dr reset bitclk sync sdata_out sdata_in wake 3.3v irqe/fp4 24.576mhz 02562-017 figure 17. interfacing ad1803 to adsp-218x dsp reset bit_clk sync sdo sdi0 sdi1 reset bit_clk sync sdata_out sdata_in chain_in primary codec id = 00 reset bit_clk sync sdata_out sdata_in g[3]/wake secondary codec id = 10 sdi pin configured for chaining g[2] reset bit_clk sync sdata_out sdata_in g[3]/wake secondary codec id = 01 g[2] ad1881a audio codec a d1803 handset codec ad1803 modem codec ac '97 digital controller 02562-018 figure 18. codec chaining allows several analog devices ac 97 codecs to be conn ected to one ac link controller port
ad1803 rev. a | page 29 of 32 typical initialization sequence immediately after first reset step 1: write to register 0x5c (configuration 1 register). bits[14:13]bnk1, bnk0 (register bank select). these bits should be set to 01 in preparation for step 2. bit[12]r34pm ( reset power mode select). if it is desired to have the ad1803 drive a clock out on the clk_out pin while reset is asserted, this bit must be changed from its default setting of 0 to 1, otherwise, the ad1803 is completely powered down whenever reset is asserted ( reset pin driven low). bits[11:10]xtal1, xtal0 (clock identification): if the clock presented on pin xtali is not 24.576 mhz, the default setting of these bits must be changed to identify the actual xtali frequency provided. bit[9]acsel (analog codec select). while this bit can be updated at any time, and even while the codec is enabled, it is recommended to set this bit prior to enabling the codec. this bit selects an analog codec used in conjunction with the digital codec within the ad1803. when set to 0, which is the default, the analog codec within the ad1803 is used. bit[8]adcal (adc calibration recalibration). until the codec is enabled, writes to this bit have little purpose. bit[7]clked (clk_out enable while reset is deasserted). immediately after reset is deasserted ( reset pin driven high) this bit is always reset to a 1. this enables the clk_out pin to provide a buffered version of the clock received on the xtali pin following every deassertion of reset . therefore, to stop this clock low and save power, this bit must be set to 0 after every deassertion of reset . stopping clk_out saves about 1.5 ma plus any addition current saved by not driving the board load that might be present. note that clk_out can also be permanently three-stated using bits cos2 to cos0 in register 0x64 bank 1. bit[6]clkea (clk_out enable while reset is asserted). this bit must be changed from its default of 0 to 1 if it is desired to have the clk_out pin provide a clock output while the ad1803 is reset ( reset pin driven low). note that bit r34pm can override the behavior selected by the state of this bit. step 2: write to register 0x64 (bank 1clock pad control register). bit[3]xtlp (crystal oscillator low power mode enable). depending on board design and crystal used, this bit can be set to 1 to engage a crystal oscillator low power mode, which saves up to 0.7 ma. this mode reduces the amount of energy that an ad1803 provides to keep a crystal oscillating, but other- wise has no effect on ad1803 behavior. if a clock is driven onto the xtali pin from an external source rather than generated by a crystal connected between the xtali and xtalo pins, the optimal setting for this bit is 1, although with only a slight power benefit. bits[2:0]cos2 to cos0 (clk_out pin drive strength select). these bits should be set to select the optimal output driver strength for the clk_out pin to soften edges and reduce emi emissions. step 3: write to register 0x5e (configuration 2 register). bit[14]gpwak (g[3]/wake interrupt signal select). if an interrupt/wake output signal is desired, this bit must be changed from its default setting of 0 to 1. this enables pin 12 to serve this role rather than a default role as a general-purpose i/o pin. when serving as an interrupt/wake flag, pin 12 is driven high whenever a qualifying event has occurred. bit[13]gpmon (g[4]/monitor output select): if the monitor output feature is used, this bit must be changed from its default setting of 0 to 1. this enables pin 11 to serve this role rather than a default role as a general-purpose i/o pin. when serving as a monitor output, pin 11 outputs a - bit stream consisting of a selectable mix of the signals present on the adc and dac channels. bit[12]gpmic (gpi[1]/mic input select). if a second select- able adc input source is desired, the setting of this bit must be changed from its default of 0 to 1. this switches the role of pin 15 from a general-purpose input flag to an analog mic input. bit[11], bit[10], bit[9], bit[7] , and bit[6]spchn, spgbp, spdss, spdl1, and spdl0. these bits affect the operation of the ad1803 only if in an ac '97 serial interface mode. bit[8]spiso (serial port isolate). see the typical codec power-down sequence section for further details. step 4: read register 0x60 (bank 1gpio initial states register). as reset is deasserted ( reset pin driven high), the first time after power is applied to the ad1803, the states of all general- purpose i/o pins are sampled and stored in this register. while the sampled states of gpio pin 2 and pin 3 are used by the ad1803 to determine serial interface mode, all remaining gpio pins are available for use, if beneficial, as identification bits to a host software. step 5: write to register 0x4c through register 0x54 (gpio control registers).
ad1803 rev. a | page 30 of 32 these registers determine the behavior of the gpio pins of the ad1803. after power is first applied to the ad1803, all gpio pins default as inputs, but with weak (~100 a) pull-up devices within the part enabled to pull any floated gpio pins high. as needed, these pins can be reconfigured to serve as interrupt sources, active high or low, sticky or unsticky, or general-purpose outputs with open-drain or cmos drivers. the weak pull-up device can also be disabled to save power. the settings of these registers, like most registers within the ad1803, are unaffected by a reset and are set to their defaults only when power is first applied to the ad1803. the most practical order is 0x4e, 0x4c, 0x50, 0x54, and finally 0x52. step 6: write to register 0x40 (line dac/adc sample rate control register) and register 0x46 (dac/adc level control register). these registers determine the codec sample rate and channel attenuation levels. while these register can be updated at any time, including while the codec is enabled, establishing desired settings prior to enabling the codec is recommended. typical codec power-up sequence step 7: write to register 0x3e (extended status and control register). bit[11]dpdn (dac power-down). this bit must be set to 0 for the dac codec channel of the ad1803 to be enabled. while this bit is set to 1 (default), all dac resources within the part are powered down and all data words sent to the ad1803 over the serial interface are ignored. when this bit is set to 0, the digital dac resources within the part are powered up. the analog dac resources within the part are powered up only if the voltage reference of the ad1803 is powered up (bit vpdn in this register is set to 0), and the analog codec of the ad1803 is selected as the partner to the digital codec of the part (bit acsel in register 0x5c is set to 0). bit[10]apdn (adc power-down): this bit should be set to 0 for the adc codec channel of the part to be enabled. while this bit is set to 1 (default), all adc resources within the ad1803 are powered down, and all data words sent out of the part over the serial interface are set to midscale (zero). when this bit is set to 0, the digital adc resources within the ad1803 are powered up. the analog adc resources within the part are powered up only if the voltage reference of the ad1803 is powered up (bit vpdn in this register is set to 0), and the analog codec of the ad1803 is selected as the partner to the digital codec of the part (bit acsel in register 0x5c is set to 0). each time the analog codec of the ad1803 is powered up, an adc calibration is automatically initiated. this calibration requires approximately 104 sample periods (defined by register 0x40), but cant be started until after the voltage reference of the part is powered up (by setting bit vpdn to 0). the voltage reference requires about 48 ms to start up. bit vsta in this register can be polled first to determine if the voltage reference is powered up, and then bit adcal in register 0x5c can be polled to determine if calibration is completed. during calibration, the codec sample rate (register 0x40) and adc source and gain levels (bit ads, bit adg20, and bit adl[3:0] in register 0x46) must not be changed. bit[9]vpdn (voltage reference power-down). if the analog codec of the ad1803 is used, this bit must be set to 0 to power up the parts voltage reference. until the voltage reference is powered up, the analog codec channels of the ad1803 ignore the setting of bit apdn and bit dpdn and remain powered down. once this bit is set to 0, approximately 48 ms are necessary to power up the voltage reference. bit vsta in this register can be polled to monitor the status of the voltage reference. bit[8]gpdn (gpio power-down). contrary to this bits name, its setting has no effect on the operation of the ad1803 when configured in dsp mode. when the ad1803 is configured in an ac '97 mode, this bit must be set to 0 for slot 12 to access gpio pins. bit[3]dsta (dac status). this bit exists solely for ac '97 compatibility. its purpose is to provide a handshake for dac power-up/power-down status changes initiated by writes to bit dpdn. however, because the ad1803 responds to a write of bit dpdn prior to it being possible to read this bit in a following serial interface frame, there is no reason to poll this status bit. bit[2]asta (adc status). this bit exists solely for ac '97 compatibility. its purpose is to provide a handshake for adc power-up/power-down status changes initiated by writes to bit apdn. because the ad1803 responds to a write of bit apdn prior to it being possible to read this bit in a following serial interface frame, there is no reason to poll this status bit. bit[1]vsta (voltage reference status). this bit can be polled to monitor the status of the voltage reference. when read as a 0, the voltage reference is either powered down or in the process of powering up. when read as a 1, the voltage reference is either powered up or in the process of powering down. approximately 48 ms after vpdn is set to a 0, this bit transitions from a 0 to a 1 indicating that the voltage reference is powered up.
ad1803 rev. a | page 31 of 32 bit[0]gsta (gpio status). this bit exists solely for ac '97 compatibility. its purpose is to provide a handshake for power- up/power-down status changes initiated by writes to bit gpdn. because the ad1803 responds to a write of bit gpdn prior to it being possible to read this bit in a following serial interface frame, there is no reason to poll this status bit. step 8: write to register 0x5c (configuration 1 register). the purpose of this write is to change the register bank selection in preparation for step 9. the value written to register 0x5c at this time should be identical to the value from step 1, except with bits[14:13] (bnk1, bnk0) set to 10. step 9: write to register 0x62 bank 2 (monitor output control register). writes to this register have no purpose unless a pin has been assigned to serve as a monitor output (see step 3 in the typical initialization sequence immediately after first section). this register can be written to power up and power down the monitor channel, select the mix of adc and dac channels delivered to the monitor output, and select the order of the - monitor output bit stream. typical codec power-down sequence there are two ways to power down the codec. the first way is to simply assert reset (drive reset pin low). this clears register 0x3e to its initial power-up default, powering down the adc, dac, and voltage reference of the ad1803. a second method is outlined below. step 1: write to register 0x3e (extended status and control register). bit[11]dpdn (dac power-down). this bit must be set to 1 to power down the dac channel of the ad18103. bit[10]apdn (adc power-down). this bit must be set to 1 to power down the adc channel of the ad18103. bit[9]vpdn (voltage reference power-down). this bit can be set to 1 to power down the voltage reference of the ad1803 and save approximately 200 a, but it can be desirable to leave the voltage reference powered up. leaving it powered up saves about 48 ms from a future codec power-up sequence, and avoids potential clicks caused by the dac output tracking the voltage reference as it falls to 0 volts when powered down, and rises to ~1.25 v when powered back up. bit[8]gpdn (gpio power-down). this bit can be set to any value because it has no effect on ad1803 operation when in dsp mode. bit[1]vsta (voltage reference status). this bit can be polled to determine the status of the parts voltage reference. when read as a 0, the voltage reference is either powered down or in the process of powering up. when read as a 1, the voltage reference is either powered up or in the process of powering down. within 0.8 ms after vpdn is set to 0, this bit transitions from 1 to 0, indicating that the voltage reference is completely powered down. if a clock is driven onto the xtali pin, and it is desired to stop this clock for additional system power savings, this clock must not be stopped until after this bit falls to a 0. typical chip power-down sequence once the codec is powered down to the level desired, no add- itional power can be saved unless the ad1803 receives a reset , ignoring power potentially saved by stopping the clock on the clk_out pin or disabling gpio pin drivers, which have resistive loads. when a reset is received by the ad1803, the serial interface automatically powers down, leaving the internal clock generation and distribution circuitry of the part as the final significant power consumer to be addressed. if bit r34pm in register 0x5c is set to a 0 before reset is asserted, this clock circuitry is powered down as well when reset is asserted, with the consequence that wake-up on ring and ability to source a clock on the clk_out pin during reset is lost. this leaves silicon leakage current, typically less than 100 a, plus inadvertent serial interface loading as the final power drains. inadvertent serial interface loading can be due to either the ad1803 receiving intermediate or switching logic levels on its bit_clk, sync, or sdata_out input pins, or the presence of resistive loads to a potential other than dgnd (ad1803 digital ground) on the sdata_in or bit_clk output pins. this inadvertent serial interface loading can be eliminated if bit spiso (serial port isolate) in register 0x5e is set to 1 before the part receives a reset with the consequence that output bit_clk is driven low weakly (<200 a drive current) whenever reset is asserted.
ad1803
outline dimensions
7.90 7.80 7.70 24 13 4.50 4.40 4.30 6.40 bsc 1 12 pin 1 0.65 1.20 bsc max 0.15 0.05 0.30 0.19 0.20 0.09 0.75 0.60 0.45 8 0 seating plane 0.10 coplanarity compliant to jedec standards mo-153-ad fig u re 1 9 . 24-l e ad thin shr i nk s m a l l outlin e p a ck age [t ssop]
(r u - 24)
dim e nsio ns sho w n i n mi ll im e t er s
ordering guide model t e mper a tur e r a nge p a ck age descri ption p a ck age o p tion ad1803jru-ree l ad1803jruz - re el 1 0c to +70c 0c to +70c 24-l e ad thin sh r i nk small o utli n e p a ck age [ t ssop] 24-l e ad thin sh r ink small o utli n e p a ck age [ t ssop] ru-24 ru-24 1 z = pb-free part. ?2006 a n alo g devi ces, inc. all rights reserve d . tra d ema r ks and registered tra d emar ks are the prop erty of their respective owners . c02562-0-1 2/06(a) rev. a | page 32 of 32

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